[U-Boot-Users] [PATCH] TQM85xx: add support for boards with > 128 MiB NOR flash memory

Martin Krause martin.krause at tqs.de
Mon Jun 25 14:56:23 CEST 2007


Some TQM85xx boards could be equipped with up to 1 GiB (NOR) flash
memory. The current memory map only supports up to 128 MiB flash.
This patch adds the configuration option CONFIG_TQM_BIGFLASH. If
set, up to 1 GiB flash is supported. To achieve this, the memory
map has to be adjusted in great parts (for example the CCSRBAR is
moved from 0xE0000000 to 0xA0000000).

If you want to boot Linux with CONFIG_TQM_BIGFLASH set, the new 
memory map also has to be considered in the kernel (changed
CCSRBAR address, changed PCI IO base address, ...)!  

Signed-off-by: Martin Krause <martin.krause at tqs.de>
---

 board/tqm85xx/init.S      |  166 +++++++++++++++++++++++++++++++++++++++++++++
 include/configs/TQM85xx.h |   42 +++++++++++
 2 files changed, 207 insertions(+), 1 deletions(-)

diff --git a/board/tqm85xx/init.S b/board/tqm85xx/init.S
index 1f61038..77fed5b 100644
--- a/board/tqm85xx/init.S
+++ b/board/tqm85xx/init.S
@@ -62,9 +62,174 @@
 tlb1_entry:
 	entry_start
 
+#ifdef CONFIG_TQM_BIGFLASH /* for TQM85xx boards with >128 MiB NOR Flash */
 	/*
 	 * Number of TLB0 and TLB1 entries in the following table
 	 */
+	.long 14
+
+	/*
+	 * TLB0		16K	Cacheable, non-guarded
+	 * 0xd001_0000	16K	Temporary Global data for initialization
+	 *
+	 * Use four 4K TLB0 entries.  These entries must be cacheable
+	 * as they provide the bootstrap memory before the memory
+	 * controler and real memory have been configured.
+	 *
+	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+	 * and must not collide with other TLB0 entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+
+	/*
+	 * TLB 0,1,2,3:	1G	Non-cacheable, guarded
+	 * 0xC0000000	1G	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	.long TLB1_MAS0(1, 3, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+	.long TLB1_MAS0(1, 2, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+	.long TLB1_MAS0(1, 1, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE + 0x20000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE + 0x20000000),
+			0,0,0,0,0,1,0,1,0,1)
+	.long TLB1_MAS0(1, 0, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE + 0x30000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE + 0x30000000),					0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	.long TLB1_MAS0(1, 4, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 5:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 5, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 6:	256M	Non-cacheable, guarded
+	 * 0xb0000000	256M	Rapid IO MEM
+	 */
+	.long TLB1_MAS0(1, 6, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 7:	64M	Non-cacheable, guarded
+	 * 0xa000_0000	1M	CCSRBAR
+	 * 0xa200_0000	16M	PCI1 IO
+	 */
+	.long TLB1_MAS0(1, 7, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 8+9:	512M	DDR, cache disabled (needed for memory test)
+	 * 0x00000000  512M	DDR System memory
+	 * Without SPD EEPROM configured DDR, this must be setup manually.
+	 * Make sure the TLB count at the top of this table is correct.
+	 * Likely it needs to be increased by two for these entries.
+	 */
+	.long TLB1_MAS0(1, 8, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+	.long TLB1_MAS0(1, 9, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,1,0,1,0,1)
+
+	entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000	   0x7fff_ffff	   DDR			   2G
+ * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
+ * 0xa000_0000	   0xa00f_ffff	   CCSR			   1M
+ * 0xa200_0000	   0xa2ff_ffff	   PCI1 IO		   16M
+ * 0xf800_0000	   0xf80f_ffff	   BCSR 		   1M	MKR: ???
+ * 0xb000_0000	   0xbfff_ffff	   RapidIO		   256M
+ * 0xc000_0000	   0xffff_ffff	   FLASH		   1G
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0	(LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR2 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff)
+#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_1G))
+
+#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
+#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+/*
+ * Rapid IO at 0xc000_0000 for 512 M
+ */
+#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
+#define LAWAR4	(LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#else /* ! CONFIG_TQM_BIGFLASH */
+		/*
+	 * Number of TLB0 and TLB1 entries in the following table
+	 */
 	.long 13
 
 	/*
@@ -223,6 +388,7 @@ tlb1_entry:
 #define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
 #define LAWAR4	(LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
 
+#endif /* CONFIG_TQM_BIGFLASH */
 
 	.section .bootpg, "ax"
 	.globl	law_entry
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index 35bfb00..9e377c4 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -44,6 +44,16 @@
 #define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/
 
 /*
+ * Configuration for big NOR Flashes.
+ *
+ * Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR
+ * Flash. Please be aware, that this changes the whole memory map (new CCSRBAR
+ * adress, ...). You have to use an adapted Linux kernel if this option is
+ * set.
+ */
+#undef CONFIG_TQM_BIGFLASH
+
+/*
  * Only MPC8540 doesn't have CPM module
  */
 #ifndef CONFIG_MPC8540
@@ -86,7 +96,11 @@
  * actual resources get mapped (not physical addresses)
  */
 #define CFG_CCSRBAR_DEFAULT	0xFF700000	/* CCSRBAR Default	*/
+#ifdef CONFIG_TQM_BIGFLASH
+#define CFG_CCSRBAR		0xA0000000	/* relocated CCSRBAR	*/
+#else
 #define CFG_CCSRBAR		0xE0000000	/* relocated CCSRBAR	*/
+#endif /* CONFIG_TQM_BIGFLASH */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
 /*
@@ -109,17 +123,29 @@
 /*
  * Flash on the Local Bus
  */
+#ifdef CONFIG_TQM_BIGFLASH
+#define CFG_FLASH0		0xE0000000
+#define CFG_FLASH1		0xC0000000
+#else
 #define CFG_FLASH0		0xFC000000
 #define CFG_FLASH1		0xF8000000
+#endif /* CONFIG_TQM_BIGFLASH */
 #define CFG_FLASH_BANKS_LIST	{ CFG_FLASH1, CFG_FLASH0 }
 
 #define CFG_LBC_FLASH_BASE	CFG_FLASH1	/* Localbus flash start	*/
 #define CFG_FLASH_BASE		CFG_LBC_FLASH_BASE /* start of FLASH	*/
 
+#ifdef CONFIG_TQM_BIGFLASH
+#define CFG_BR0_PRELIM		0xE0001801	/* port size 32bit	*/
+#define CFG_OR0_PRELIM		0xE0000040	/* 512MB Flash		*/
+#define CFG_BR1_PRELIM		0xC0001801	/* port size 32bit	*/
+#define CFG_OR1_PRELIM		0xE0000040	/* 512MB Flash		*/
+#else
 #define CFG_BR0_PRELIM		0xfc001801	/* port size 32bit	*/
 #define CFG_OR0_PRELIM		0xfc000040	/* 64MB Flash		*/
 #define CFG_BR1_PRELIM		0xf8001801	/* port size 32bit	*/
 #define CFG_OR1_PRELIM		0xfc000040	/* 64MB Flash		*/
+#endif /* CONFIG_TQM_BIGFLASH */
 
 #define CFG_FLASH_CFI				/* flash is CFI compat.	*/
 #define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver*/
@@ -141,9 +167,14 @@
 
 #define CONFIG_L1_INIT_RAM
 #define CFG_INIT_RAM_LOCK	1
+#ifdef CONFIG_TQM_BIGFLASH
+#define CFG_INIT_RAM_ADDR	0xa4010000	/* Initial RAM address	*/
+#else
 #define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address	*/
+#endif /* CONFIG_TQM_BIGFLASH */
 #define CFG_INIT_RAM_END	0x4000		/* End used area in RAM	*/
 
+
 #define CFG_GBL_DATA_SIZE	128		/* num bytes initial data*/
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
@@ -227,9 +258,14 @@
 #define CFG_DTT_HYSTERESIS	3
 
 /* RapidIO MMU */
+#ifdef CONFIG_TQM_BIGFLASH
+#define CFG_RIO_MEM_BASE	0xb0000000	/* base address		*/
+#define CFG_RIO_MEM_SIZE	0x10000000	/* 256M			*/
+#else
 #define CFG_RIO_MEM_BASE	0xc0000000	/* base address		*/
-#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
 #define CFG_RIO_MEM_SIZE	0x20000000	/* 128M			*/
+#endif /* CONFIG_TQM_BIGFLASH */
+#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
 
 /*
  * General PCI
@@ -238,7 +274,11 @@
 #define CFG_PCI1_MEM_BASE	0x80000000
 #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
 #define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M			*/
+#ifdef CONFIG_TQM_BIGFLASH
+#define CFG_PCI1_IO_BASE	0xa2000000
+#else
 #define CFG_PCI1_IO_BASE	0xe2000000
+#endif /* CONFIG_TQM_BIGFLASH */
 #define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
 #define CFG_PCI1_IO_SIZE	0x1000000	/* 16M			*/
 




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