[U-Boot-Users] BITBANGMII implementation for MPC8548 eTSEC && 88E1111
samsongshu at yahoo.com.cn
Wed Mar 7 10:56:44 CET 2007
Ben Warren <bwarren at qstreams.com> wrote:
> Time to reach into your engineering tool bag.
> controllers, coupling is loose. You should be able to bitbang this
> provided the physical wires exist between the CPLD and the PHY. I
> guess white-wiring the TSEC's MDC line isn't an option?
I did wire two CPLD GPIOs to MDC/MDIO of PHY.
> Stylistically, this leaves a lot to be desired, but if register 83
> (better to use hex here) really maps to the MDC and MDIO pins, it
> should work.
Good catch. I did mistake 0x83 for 83:-(
> > Am I on the right track?
> Before messing with the TSEC driver, try talking with the PHY using
> the 'mii' U-boot commands. Also, pull out your oscilloscope and
> check that the lines are toggling as you want. Once you're confident
> Bitbanged-MII works, integrate it into TSEC.
This is really a nice debug method. With it, we found that PHY
MDIO output HIGH level was too low - less than 1.5V. So CPLD took
it as '0' always. We pulled up it to 3.3V via a resistor and
changed CPLD internal bank power supply level as 2.5/1.8V but
no luck. Now hardware colleagues help us to work out another
way to solve it.
As the HIGH-Performance processors comes out, there is an extra
workload to debug those broken board besides normal development.
No easy to drop it as before. Luckily, u-boot's rich features
and the poweful resources make it easier than it should be.
Thanks a lot,
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