[U-Boot-Users] [PATCH]Fix two bugs for MPC83xx DDR2 controller SPD Init

[Xie Xiaobo]

There are a few bugs in the cpu/mpc83xx/spd_sdram.c
the first bug is that the picos_to_clk routine introduces a huge 
rounding error in 83xx.
the second bug is that the mode register write recovery field is
tWR-1, not tWR >> 1. 

---
This patch applies to the mpc83xx branch of the opensource.freescale.com u-boot-83xx.git tree

 cpu/mpc83xx/spd_sdram.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index d9b8753..869dab4 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -58,8 +58,8 @@ picos_to_clk(int picos)
 	int clks;
 
 	ddr_bus_clk = gd->ddr_clk >> 1;
-	clks = picos / ((1000000000 / ddr_bus_clk) * 1000);
-	if (picos % ((1000000000 / ddr_bus_clk) * 1000) != 0)
+	clks = picos / (1000000000 / (ddr_bus_clk / 1000));
+	if (picos % (1000000000 / (ddr_bus_clk / 1000)) != 0)
 		clks++;
 
 	return clks;
@@ -624,7 +624,7 @@ long int spd_sdram()
 			 | (1 << (16 + 10))             /* DQS Differential disable */
 			 | (add_lat << (16 + 3))        /* Additive Latency in EMRS1 */
 			 | (mode_odt_enable << 16)      /* ODT Enable in EMRS1 */
-			 | ((twr_clk >> 1) << 9)        /* Write Recovery Autopre */
+			 | ((twr_clk - 1) << 9)         /* Write Recovery Autopre */
 			 | (caslat << 4)                /* caslat */
 			 | (burstlen << 0)              /* Burst length */
 			);
-- 
1.4.4.1