[U-Boot-Users] [patch] Fix clock calculation for S3C2410 cpu

[Martin Krause]

Fix clock calculation for S3C2410 cpu.

The S3C2410 cpu has a new bit in the CLKDIV register, which is now interpreted
correctly (for a clock ratio of 1:4:4).

Signed-off-by: Martin Krause <martin.krause at tqs.de>

---
commit c31f5dcfea535dc396ef125a2d3bf990ee7b2ca2
tree d219974afd18173e71f4da1a5791a43a0be964f9
parent 070589479993994f747aa0ee50d5ab037eaf0511
author Martin Krause <martin.krause at tqs.de> Fri, 05 Jan 2007 09:42:09 +0100
committer Martin Krause <martin.krause at tqs.de> Fri, 05 Jan 2007 09:42:09 +0100

 cpu/arm920t/s3c24x0/speed.c |   14 ++++++++++++--
 1 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/cpu/arm920t/s3c24x0/speed.c b/cpu/arm920t/s3c24x0/speed.c
index e0dca62..4f354d6 100644
--- a/cpu/arm920t/s3c24x0/speed.c
+++ b/cpu/arm920t/s3c24x0/speed.c
@@ -30,7 +30,7 @@
  */
 
 #include <common.h>
-#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
+#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410)
 
 #if defined(CONFIG_S3C2400)
 #include <s3c2400.h>
@@ -81,6 +81,11 @@ ulong get_HCLK(void)
 {
     S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
 
+#ifdef CONFIG_S3C2410
+    if (clk_power->CLKDIVN & 0x4)
+	    return get_FCLK()/4;
+    else
+#endif
     return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
 }
 
@@ -89,6 +94,11 @@ ulong get_PCLK(void)
 {
     S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
 
+#ifdef CONFIG_S3C2410
+    if (clk_power->CLKDIVN & 0x4)
+	    return get_FCLK()/4;
+    else
+#endif
     return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK());
 }
 
@@ -98,4 +108,4 @@ ulong get_UCLK(void)
     return(get_PLLCLK(UPLL));
 }
 
-#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
+#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) */
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