[U-Boot-Users] "6.at91rm9200":(1 of 1) [PATCH][ARM] Initialize at91rm9200 board (and set LED)
Ulf Samuelsson
ulf at atmel.com
Tue Mar 27 18:16:08 CEST 2007
Author: Ulf Samuelsson <ulf at atmel.com>
Date: 2007-03-27
Subject: "6.at91rm9200":(1 of 1) [PATCH][ARM] Initialize at91rm9200 board (and set LED)
CHANGELOG:
[PATCH][ARM] Initialize at91rm9200 board (and set LED)
Boot at91rm9200 from parallel flash if CONFIG_BOOTBINFUNC is set
Define some constants needed to use at91rm9200dk/ek LEDs
Add initialization similar to Atmel boot.bin
Make sure things initialized by dataflashboot.bin
does not get initialized again in u-boot
Patch generated from files:
cpu_arm920t_start.S.patch
include_asm-arm_arch-at91rm9200_AT91RM9200.h.patch
Signed-off-by: Ulf Samuelsson
---------------------------------------------------------------------------------------------------------------------------------
diff -urN u-boot-1.2.0/cpu/arm920t/start.S u-boot-1.2.0-atmel/cpu/arm920t/start.S
--- u-boot-1.2.0/cpu/arm920t/start.S 2007-01-07 00:13:11.000000000 +0100
+++ u-boot-1.2.0-atmel/cpu/arm920t/start.S 2007-03-24 20:07:32.000000000 +0100
@@ -27,7 +27,9 @@
#include <config.h>
#include <version.h>
-
+#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
+#include <led.h>
+#endif
/*
*************************************************************************
@@ -116,6 +118,68 @@
orr r0,r0,#0xd3
msr cpsr,r0
+#if CONFIG_AT91RM9200
+#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
+ bl LED_init
+ bl red_LED_on
+#endif
+
+#ifdef CONFIG_BOOTBINFUNC
+/* code based on entry.S from ATMEL */
+#define AT91C_BASE_CKGR 0xFFFFFC20
+#define CKGR_MOR 0
+ /* Get the CKGR Base Address */
+ ldr r1, =AT91C_BASE_CKGR
+
+/* Main oscillator Enable register APMC_MOR : Enable main oscillator , OSCOUNT = 0xFF */
+/* ldr r0, = AT91C_CKGR_MOSCEN:OR:AT91C_CKGR_OSCOUNT */
+ ldr r0, =0x0000FF01
+ str r0, [r1, #CKGR_MOR]
+ /* Add loop to compensate Main Oscillator startup time */
+ ldr r0, =0x00000010
+LoopOsc:
+ subs r0, r0, #1
+ bhi LoopOsc
+ /* scratch stack */
+ ldr r1, =0x00204000
+ /* Insure word alignment */
+ bic r1, r1, #3
+ /* Init stack SYS */
+ mov sp, r1
+ /*
+ * This does a lot more than just set up the memory, which
+ * is why it's called lowlevelinit
+ */
+ bl lowlevelinit /* in memsetup.S */
+ bl icache_enable;
+ /*------------------------------------
+ Read/modify/write CP15 control register
+ -------------------------------------
+ read cp15 control register (cp15 r1) in r0
+ ------------------------------------*/
+ mrc p15, 0, r0, c1, c0, 0
+ /* Reset bit :Little Endian end fast bus mode */
+ ldr r3, =0xC0000080
+ /* Set bit :Asynchronous clock mode, Not Fast Bus */
+ ldr r4, =0xC0000000
+ bic r0, r0, r3
+ orr r0, r0, r4
+ /* write r0 in cp15 control register (cp15 r1) */
+ mcr p15, 0, r0, c1, c0, 0
+#endif /* CONFIG_BOOTBINFUNC */
+ /*
+ * relocate exeception table
+ */
+ ldr r0, =_start
+ ldr r1, =0x0
+ mov r2, #16
+copyex:
+ subs r2, r2, #1
+ ldr r3, [r0], #4
+ str r3, [r1], #4
+ bne copyex
+#endif
+
/* turn off the watchdog */
#if defined(CONFIG_S3C2400)
# define pWTCON 0x15300000
@@ -160,6 +224,26 @@
bl cpu_init_crit
#endif
+#ifdef CONFIG_AT91RM9200
+#ifdef CONFIG_BOOTBINFUNC
+relocate: /* relocate U-Boot to RAM */
+ adr r0, _start /* r0 <- current position of code */
+ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
+ cmp r0, r1 /* don't reloc during debug */
+ beq stack_setup
+
+ ldr r2, _armboot_start
+ ldr r3, _bss_start
+ sub r2, r3, r2 /* r2 <- size of armboot */
+ add r2, r0, r2 /* r2 <- source end address */
+
+copy_loop:
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end addreee [r2] */
+ ble copy_loop
+#endif /* CONFIG_BOOTBINFUNC */
+#else
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
@@ -178,7 +262,7 @@
cmp r0, r2 /* until source end addreee [r2] */
ble copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
-
+#endif
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
@@ -262,7 +346,11 @@
* find a lowlevel_init.S in your board directory.
*/
mov ip, lr
- bl lowlevel_init
+#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
+
+#else
+ bl lowlevel_init
+#endif
mov lr, ip
mov pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff -urN u-boot-1.2.0/include/asm-arm/arch-at91rm9200/AT91RM9200.h u-boot-1.2.0-atmel/include/asm-arm/arch-at91rm9200/AT91RM9200.h
--- u-boot-1.2.0/include/asm-arm/arch-at91rm9200/AT91RM9200.h 2007-01-07 00:13:11.000000000 +0100
+++ u-boot-1.2.0-atmel/include/asm-arm/arch-at91rm9200/AT91RM9200.h 2007-03-24 20:07:32.000000000 +0100
@@ -692,11 +692,15 @@
#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */
#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */
+#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) /* Pin Controlled by PB3 */
+#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB3 */
+#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) /* Pin Controlled by PB3 */
#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) /* Pin Controlled by PB3 */
#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) /* Pin Controlled by PB4 */
#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB5 */
#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */
#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */
+#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) /* Pin Controlled by PB22 */
#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */
#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */
#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */
@@ -737,19 +741,36 @@
#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */
#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) /* (PIOC) Pin Data Status Register */
-#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */
-#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */
+#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) /* (AIC) Base Address */
+#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */
+#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */
+#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */
+#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */
+#define AT91C_BASE_PIOD ((AT91PS_PIO) 0xFFFFFA00) /* (PIOC) Base Address */
#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */
+#if 0
+#define AT91C_BASE_ST ((AT91PS_ST) 0xFFFFFD00) /* (PMC) Base Address */
+#define AT91C_BASE_RTC ((AT91PS_RTC) 0xFFFFFE00) /* (PMC) Base Address */
+#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) /* (PMC) Base Address */
+#endif
+
#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */
-#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */
+#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA4000) /* (TC0) Base Address */
+#if 0
+#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) /* (TC0) Base Address */
+#define AT91C_BASE_MCI ((AT91PS_MCI) 0xFFFB4000) /* (TC0) Base Address */
+#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) /* (TC0) Base Address */
+#endif
+#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */
+#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */
+#define AT91C_BASE_US2 ((AT91PS_USART) 0xFFFC8000) /* (US1) Base Address */
+#define AT91C_BASE_US3 ((AT91PS_USART) 0xFFFCC000) /* (US1) Base Address */
+#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */
+
#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) /* (CKGR) Base Address */
-#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */
-#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */
-#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */
#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */
#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */
-#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */
-#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */
#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */
#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */
#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */
--
Best Regards,
Ulf Samuelsson
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