Leonid Leonid at a-k-a.net
Thu May 17 04:12:38 CEST 2007

On Wednesday, May 16, 2007 4:11 PM Timur Tabi wrote:
> Leonid wrote:
> > As a matter of fact, such scheme is widely used for Xilinx FPGA
> > cores (both Microblaze and PPC) as well as for ARM CPUs. 

> Can you give me some details as to how this works?  

I am not sure what you are asking about. If the question is what RAM
booting scheme looks like - I think we've been through that already.
U-boot image is compiled to run from some place in RAM (TEXT_BASE in
config.mk makes sure of that), yet it's environment and binary shall be
on the flash. First stage bootloader fetches u-boot from there, copies
it to RAM and starts. 

Such a scheme proves to be useful when for some reason you should have a
small code, taking control over your CPU right after reset and u-boot is
too big to do the job. This is the case of CPU core running in FPGA or
ARM CPU. Yet I don't claim this is the only way to go in such cases -
the Emperor August used to say that there are many ways of skinning a
cat to which Sir Kipling added that there are 78 methods of composing
songs of tribes and all of them are correct.

Such 2 stage booting may be useless for Freescale - I don't have much
experience with it - it's certainly not needed for AMCC PPC CPUs. 

If you ask regarding specific configuration flags, all those ...RAMBOOT
- I'm not sure how to use them and suspect that in many practical cases
they are simply ignored. Look for example .h and config.mk file for
ATMEL reference board which is using 2-stage booting scheme (tiny
boot.bin is expected to be located in the beginning of flash, address


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