[U-Boot-Users] Problems writing to memory with mw

[David Hawkins]

Hi Robert,

> The bad news:  you lost the "read the manual" lottery.  :-/
> 
> [snip]
>
> The cache disable test is leveraging on the fact that, when caching is 
> disabled, the processor (tends to?) launches only one address at a time 
> and waits for the result before going on to the next address.  This 
> "papers over" the SDRAM configuration error.

If you want to probe the board for single-cycle accesses
versus burst-accesses without triggering a crash due to CPU
cache issues, I'd suggest reading the user-manual section on
the DMA controller.

You should be able to DMA a block of data from say internal
SRAM, or a device, or the local bus, to the DDR memory,
or from DDR to another location.

Were you involved with the board layout? Was a DDR voltage simulation
and timing simulation performed? In my MPC8349E design, I'm using
DDR1 SDRAM soldered to the board. The voltage and timing simulations
show that I could eliminate the VTT termination regulator due to
the short transmission lines, i.e., the ringing of the non-terminated
transmission lines was not sufficient to violate any 'rules'.
However, I will have to use a specific MPC driver output impedance,
specific source termination resistor values, and I will have to
configure the DDR1 memory for half-strength drivers. So although I
copied a lot of stuff off the MPC8349EA-MDS-PB reference board,
I will need to sit down for a few days, when I get the boards,
and get all the memory configuration correct.

Its this subtle information you require before you can have any
confidence your memory interface is working correctly. Actually,
its the simulation info you need before you even build your board
to know that its possible to get your memory interface working
correctly!

Since you are using DDR DIMMs, you have less variables. When I was
routing the DDR on the board, I looked at Micron's site and they
have DIMM design PCBs. I imagine that most DDR DIMMs either use
these PCB designs directly, or are virtually identical.
Kingston memory is pretty good, I've used it and had no problems
in desktop machines.

If your design uses DDR2, then it has on-chip terminations, so the
board design/layout would have been a little simpler than DDR1.
I used DDR1 since it uses 2.5V and I needed that voltage elsewhere.
However, all the traces on the board would have required careful
length matching to operate at DDR speeds of 333MHz+.

What clock frequency are you trying to run the DDR at for your
tests? If you back-off to a slower clock frequency, you open
up the setup/hold windows and provide yourself a little more
timing margin. The MPC8349E has a delay register for launching
address/controls at various delays, so you could try that same
control on your processor to adjust the address/control timing
too.

Although, given that your issue is related to bursting, I'd be
more suspicious of data bus waveforms or the timing of the burst
data. A scope or DDR2 DIMM logic analyzer probe would be useful.

For probing data, you'll want to look at the timing of the
DQ signals relative to the DQS (strobe) signal, and DM (mask).
Those are the DDR1 names, I think DDR2 is the same, but the
DQS signals can be differential.

Cheers,
Dave