[U-Boot-Users] 85xx pci problems
robert lazarski
robertlazarski at gmail.com
Fri Nov 30 15:07:28 CET 2007
Hi all,
On our custom 8548, at the moment our priority is bringing up PCI for
the first time. However, we can't get any cards recognized. To be
honest, I found the device tree and TLB code of PCI to be the hardest
part of the coding of the port, and I may have problems. We have a
PCI1, PCI2 and one PCIE. Furthermore, since this is a new board we may
have hardware issues.
>From the u-boot monitor off of the latest git, I'm getting this:
=> pci
Scanning PCI devices on bus 0
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
00.00.00 0x1057 0x0012 Processor 0x20
=> pci long
Scanning PCI devices on bus 0
Found PCI device 00.00.00:
vendor ID = 0x1057
device ID = 0x0012
command register = 0x0006
status register = 0x20b0
revision ID = 0x20
class code = 0x0b (Processor)
sub class code = 0x20
programming interface = 0x00
cache line = 0x08
latency time = 0x80
header type = 0x00
BIST = 0x00
base address 0 = 0x00000000
base address 1 = 0x00000000
base address 2 = 0x00000004
base address 3 = 0x00000000
base address 4 = 0x0000000c
base address 5 = 0x00000000
cardBus CIS pointer = 0x00000000
sub system vendor ID = 0x0000
sub system ID = 0x0000
expansion ROM base address = 0x00000000
interrupt line = 0x00
interrupt pin = 0x01
min Grant = 0x00
max Latency = 0x00
=> pci 1 long
Scanning PCI devices on bus 1
Found PCI device 01.00.00:
vendor ID = 0x1057
device ID = 0x0012
command register = 0x0006
status register = 0x20a0
revision ID = 0x20
class code = 0x0b (Processor)
sub class code = 0x20
programming interface = 0x00
cache line = 0x08
latency time = 0x80
header type = 0x00
BIST = 0x00
base address 0 = 0x00000000
base address 1 = 0x00000000
base address 2 = 0x00000004
base address 3 = 0x00000000
base address 4 = 0x0000000c
base address 5 = 0x00000000
cardBus CIS pointer = 0x00000000
sub system vendor ID = 0x0000
sub system ID = 0x0000
expansion ROM base address = 0x00000000
interrupt line = 0x00
interrupt pin = 0x01
min Grant = 0x00
max Latency = 0x00
>From linux I get:
bash-3.00# lspci -vv
00:00.0 Class 0b20: 1057:0012 (rev 20)
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR+ FastB2B-
Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort+ >SERR- <PERR-
Latency: 128, Cache Line Size 08
Interrupt: pin A routed to IRQ 19
Region 1: Memory at <unassigned> (32-bit, prefetchable)
Region 2: Memory at <unassigned> (64-bit, non-prefetchable)
Region 4: Memory at <unassigned> (64-bit, non-prefetchable)
Capabilities: [60] #00 [0000]
Not sure why I get "Status: Cap+ 66Mhz" - I need 33mhz and my device
tree has "clock-frequency = <1fca055>". My device tree is mapped to
have PCI at the root level to match the current 2.6.24RC2 . I've coded
my TLB's to match this device tree:
pci at e0008000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 J17 Slot 1 */
8800 0 0 1 &mpic 2 1
8800 0 0 2 &mpic 3 1
8800 0 0 3 &mpic 4 1
8800 0 0 4 &mpic 1 1
/* IDSEL 0x12 J16 Slot 2 */
9000 0 0 1 &mpic 3 1
9000 0 0 2 &mpic 4 1
9000 0 0 3 &mpic 2 1
9000 0 0 4 &mpic 1 1>;
interrupt-parent = <&mpic>;
interrupts = <4 2>;
bus-range = <0 ff>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <1fca055>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008000 1000>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
};
pci at e000c000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 J17 Slot 1 */
8800 0 0 1 &mpic 2 1
8800 0 0 2 &mpic 3 1
8800 0 0 3 &mpic 4 1
8800 0 0 4 &mpic 1 1
/* IDSEL 0x12 J16 Slot 2 */
9000 0 0 1 &mpic 3 1
9000 0 0 2 &mpic 4 1
9000 0 0 3 &mpic 2 1
9000 0 0 4 &mpic 1 1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
bus-range = <0 ff>;
ranges = <02000000 0 c0000000 c0000000 0 20000000
01000000 0 00000000 e2800000 0 00100000>;
clock-frequency = <1fca055>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e000c000 1000>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
};
pcie at e000a000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 (PEX) */
00000 0 0 1 &mpic 0 1
00000 0 0 2 &mpic 1 1
00000 0 0 3 &mpic 2 1
00000 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <1a 2>;
bus-range = <0 ff>;
ranges = <02000000 0 a0000000 a0000000 0 20000000
01000000 0 00000000 e3000000 0 08000000>;
clock-frequency = <1fca055>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e000a000 1000>;
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
pcie at 0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <02000000 0 a0000000
02000000 0 a0000000
0 20000000
01000000 0 00000000
01000000 0 00000000
0 08000000>;
};
};
We are putting the o-scope on the board to look for hardware issues.
Any help on what to look for concerning PCI hardware issues or my TLB
/ device tree issues would be highly appreciated - we're running out
of time!
Thanks,
Robert
More information about the U-Boot
mailing list