[U-Boot-Users] Low power mode in 85xx

[robert lazarski]

Hi all,

Can anyone tell me how it is possible for the e500 core to enter power
management modes very early in the u-boot code? Note here that this
session shows the MRE[WE] bit to be set in the first few lines in of
start.S - and the exact address this happens is seemingly random:

ATUM>ti
    Target CPU        : MPC85xx (e500v2 rev.2)
    Core state        : halted
    Debug entry cause : single step
    Current PC        : 0xfffff020
    Current CR        : 0x00000000
    Current MSR       : 0x00000200
    Current LR        : 0x00000000
    Current CCSRBAR   : 0x0_e0000000
ATUM>ti
- Core status is 0x0041
*** Core is stopped, no debugging possible
# PPC: timeout while waiting for halt
ATUM>    Target CPU        : MPC85xx (e500v2 rev.2)
    Core state        : halted
    Debug entry cause : COP freeze
    Current PC        : 0xfffff020
    Current CR        : 0x0105941c
    Current MSR       : 0x01064744
    Current LR        : 0x00021f3a
    Current CCSRBAR   : 0x0_e0000000
# Step timeout detected

Disassembly shows fffff020 to be way be the tlb1_entry. What is
setting this bit? My understanding is it just doesn't happen by itself
- something must be setting it right?

BDI support tells me that this has been a known issue for 85xx, and
while a fix was tested for 8560 they are unsure if the fix was ever
tested on 8548.

Thanks,
Robert