[U-Boot-Users] Debugging 85xx eTSEC's

[Clemens Koller]

robert lazarski schrieb:
> Where 'is in sgmii mode' comes from standard 85xx stuff: I can't ping
> when setting ethact to be eTSEC2, and I get this when running 'mii
> info'  :
> 
> => mii info
> PHY_PHYIDR2 @ 0x0 = 0xffff
> PHY_PHYIDR2 @ 0x1 = 0xffff
> PHY_PHYIDR2 @ 0x2 = 0xffff
> PHY_PHYIDR2 @ 0x3 = 0xffff
> Can't read PHY at address 4
> ...
> Any ideas?

As Ben mentioned already, check your hardware:
Check the hw configured PHY addresses. Then you should see at least
proper IDs when you do the mii info. PullUps on the MDC/MDIO lines?
You should be able to see some traffic there with an oscilloscope.

Then, double-check the PHY configuration and it's host interface
setting...(CONFIGx<->LEDy connections)
The MV88E1111 should work with the generic PHY initialization
since the Marvell PHYs have a quite compatible standard register set.

If you want, you can send me this part of the schematic for review.
I have the MV88E1111 on the MPC85xx working fine using GMII.

Regards,
-- 
Clemens Koller
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