[U-Boot-Users] minimum bdi config to read flash on 85xx

[David Hawkins]

> We now see the CE on the flash chip going from 3.3v to 0 on reset of
> the 8548. We also see the same behavior when issuing a mdh command on
> the bdi

Great. Thats encouraging :)

> however, we cannot see any activity whatsoever on the Ax
> pins on the spansion flash chip when trying read via the bdi and mdh.

What about when the processor boots?

 > http://www.freescale.com/files/32bit/doc/ref_manual/MPC8548ERM.pdf

p233 of the PDF:

   When the e500 core comes out of reset, its MMU has one 4-Kbyte
   page defined at 0x0_FFFF_Fnnn. The core begins execution with
   the instruction at effective address 0x0_FFFF_FFFC. To get this
   instruction, the core’s first instruction fetch is a burst read
   of boot code from effective address 0x0_FFFF_FFE0.

So the address bus LSBs should be changing during this burst,
whereas the MSBs would be high.

 > I did see RCW while googling, but that appears not to be present on
 > the 85xx as I couldn't find it in the 85xx bdi manual or the freescale
 > manual. Anyone know the equivalent?

It looks like the 85xx ditches the RCW method in favor of the
boot sequencer, which the 83xx also supports. As far as I understand
the processor comes out of reset, holds the core in reset, reads
register settings from an I2C EEPROM, programs the registers,
and then releases the core. Basically you can override any (some?)
default register settings.

p233 states:
   the default boot ROM address range defined in the MPC8548E
  (8 Mbytes at 0x0_FF80_0000 to 0x0_FFFF_FFFF

which is the same as one of the defaults for the MPC8349.

I'm pretty sure that you should be able to power up the processor,
and the BDI-2000 can play in this default address-space, i.e.,
accesses between 0xFF800000 and the end of 4GB space should
decode to the Flash.

Do you have a Freescale evaluation board for comparison tests?

Cheers,
Dave