[U-Boot-Users] minimum bdi config to read flash on 85xx
dwh at ovro.caltech.edu
Wed Sep 5 23:19:52 CEST 2007
>> Here's some notes I wrote a while back
>> Figure 5, p33, shows LA[27:31] toggling during boot from Flash.
>> Note that the asynchronous memory interface (GPCM) changes
>> address pins LA[27:31] during byte-wise access *not* the
>> LAD[27:31] multiplexed address/data bus that. So if the
>> board design connects up the wrong pins to the Flash,
>> it won't work. In your case, since you talk about LBA30
>> as being your LSB, it sound like you have 16-bit Flash.
>> The same comment applies though; LA[27:30] are the bits
>> that should be connected to the Flash for booting.
> Bingo! Excellent notes as it seems to describe our exact problem. The
> way you describe it must be done - using pins LA[27:30] in our case -
> is _not_ how our board is. It was that way in the prototype phase but
> had a spurious signal on the bus so the hardware guys say. So it was
> changed to the way you say it can't be done - via LAD[27:30]
> multiplexed address/data bus.
I'm glad we've found your problem, but I'm sorry to hear
the cause. Life now becomes more difficult for you :(
>> Note: if your Flash is connected to the wrong address pins,
>> it might be possible using the boot sequencer to change the
>> boot address to a UPM controlled area, and then use the
>> UPM to read the flash. But of course that requires having
>> the I2C EEPROM on the board to enable the boot sequencer.
> We don't have an I2C EEPROM, so its jumper wire time.
Its worth trying. My assumption would be that if you use
the I2C boot sequencer to setup the boot address (however that
is done), and then setup the memory controller that decodes
that address to trigger the use of a UPM, where the UPM is
setup correctly to read the Flash, then it will boot
correctly. Of course I've never done this, or heard of a
board that does it, so let us know how you go :)
> This is really a side issue now, but since I asked it I might as well
> finish up on it. The two 8548 boards I've looked at - EP8548 and CDS -
> both have 8MB of flash starting at FF800000. What relation does that
> have to the 8548 boot rom location of FF800000 ?
Read the explanation on p31 for the 83xx
The thing to get your head around is that (for an 83xx);
On reset the processor setups up a basic memory map
where the processor boots from either 0xFFF00100 or
0x00000100, i.e., it boots from 1MB lower than the
highest 32-bit address or it boots from address 0.
The processor sets up an 8MB memory window that decodes to
that Flash, eg. 0xFF800000 is the default base address
of that Flash, or 0x0000000 is the default.
(Assuming of course the config words say to boot from
local bus flash).
When you have an 8MB flash, either boot base-address works
fine. However, when you have a larger flash, high-boot
requires the boot code reside about 8MB into your Flash.
Thats a bummer, as it splits your useable Flash in two,
so using low-boot works nicer.
Regardless of which boot method is used, once u-boot code
runs, it sets up the decode region for the flash to be
whereever it wants to be. In some boards, I am sure the
Flash just gets left where it is, with perhaps the memory
window being opened wider if there was a larger flash.
In that case, the u-boot code for a high-boot image would
still be found about 8MB into that decode region (for
Basically, shortly after the processor boots you setup the
memory map as you'd like to see it.
> Since I have 128MB of
> flash starting at F8000000 in my or0 / br0 registers and LAW's in my
> u-boot code, do I not need to change the boot rom location? Does this
> effect the location to load the u-boot.bin file, 0xFFF80000 in the two
> 8548 examples?
It depends :)
If your processor boot sequence depended on the default FF800000
window, and high-booted, then u-boot would live about 8MB into
your 128MB Flash, and without changing the or0/br0, you'd only
see the lower 8MB of the Flash. U-Boot would be linked with the
FF800000 base address (or whatever U-boot needs regarding addresses).
Once U-boot executes, and I think has setup the DDR and moved
over to run from DDR, its no longer executing from Flash, so the
location of the Flash can be moved. In that case, you'd change
the base address to be F8000000 and viola, you can access all
If however you use the I2C boot sequencer to setup the 128MB
flash as 128MB starting at F8000000, and boot that way, the
u-boot image will sit about 1MB from the end of the 128MB
Flash, not 8MB from the start of the flash. However, the processor
reset vector, and hence u-boot code, will execute from FFFF0100
in either case.
I haven't looked at the 85xx manual in enough detail to see if
all this applies, but thats the basics :)
If you can get the 85xx to boot from 00000000, then it won't
matter if you setup an 8MB window or 128MB window, just so long
as the window starts at address 00000000 after reset. Then you
can move it to F8000000 after boot. Then you'll only have code
at the start of Flash, not starting 8MB into it (or 1MB from
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