[U-Boot-Users] [PATCH 2/3] Apollon BSP support
Kyungmin Park
kmpark at infradead.org
Fri Sep 14 02:52:02 CEST 2007
Apollon BSP support
The Apollon based on OMAP2420 is designed for OneNAND development.
It's similar with OMAP2420 H4 except some peripherals.
Now this board is maintained at mainline kernel.
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
diff --git a/board/apollon/lowlevel_init.S b/board/apollon/lowlevel_init.S
new file mode 100644
index 0000000..380108d
--- /dev/null
+++ b/board/apollon/lowlevel_init.S
@@ -0,0 +1,340 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2005-2007
+ * Samsung Electronics,
+ * Kyungmin Park <kyungmin.park at samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/omap2420.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+#include "mem.h"
+
+#define APOLLON_CS0_BASE 0x00000000
+
+#ifdef PRCM_CONFIG_I
+#define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907
+#define SDRC_ACTIM_CTRLB_0_VAL 0x00000013
+#define SDRC_RFR_CTRL_0_VAL 0x00044C01
+#elif defined(PRCM_CONFIG_II)
+#define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485
+#define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C
+#define SDRC_RFR_CTRL_0_VAL 0x00030001
+#endif
+
+#define SDRAM_BASE_ADDRESS 0x80008000
+
+_TEXT_BASE:
+ .word TEXT_BASE /* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+
+#ifdef CFG_NOR_BOOT
+ /* Check running in SDRAM */
+ mov r0, pc, lsr #28
+ cmp r0, #8
+ beq prcm_setup
+
+flash_setup:
+ /* In Flash */
+ ldr r0, =WD2_BASE
+ ldr r1, =WD_UNLOCK1
+ str r1, [r0, #WSPR]
+
+ ldr r1, =WD_UNLOCK2
+ str r1, [r0, #WSPR]
+
+ /* Pin muxing for SDRC */
+ mov r1, #0x00
+ ldr r0, =0x480000A1 /* ball C12, mode 0 */
+ strb r1, [r0]
+
+ ldr r0, =0x48000032 /* ball D11, mode 0 */
+ strb r1, [r0]
+
+ ldr r0, =0x480000A3 /* ball B13, mode 0 */
+ strb r1, [r0]
+
+ /* SDRC setting */
+ ldr r0, =OMAP2420_SDRC_BASE
+ ldr r1, =0x00000010
+ str r1, [r0, #0x10]
+
+ ldr r1, =0x00000100
+ str r1, [r0, #0x44]
+
+ /* SDRC CS0 configuration */
+ ldr r1, =0x00d04011
+ str r1, [r0, #0x80]
+
+ ldr r1, =SDRC_ACTIM_CTRLA_0_VAL
+ str r1, [r0, #0x9C]
+
+ ldr r1, =SDRC_ACTIM_CTRLB_0_VAL
+ str r1, [r0, #0xA0]
+
+ ldr r1, =SDRC_RFR_CTRL_0_VAL
+ str r1, [r0, #0xA4]
+
+ ldr r1, =0x00000041
+ str r1, [r0, #0x70]
+
+ /* Manual command sequence */
+ ldr r1, =0x00000007
+ str r1, [r0, #0xA8]
+
+ ldr r1, =0x00000000
+ str r1, [r0, #0xA8]
+
+ ldr r1, =0x00000001
+ str r1, [r0, #0xA8]
+
+ ldr r1, =0x00000002
+ str r1, [r0, #0xA8]
+ str r1, [r0, #0xA8]
+
+ /*
+ * CS0 SDRC Mode register
+ * Burst length = 4 - DDR memory
+ * Serial mode
+ * CAS latency = 3
+ */
+ ldr r1, =0x00000032
+ str r1, [r0, #0x84]
+
+ /* Note: You MUST set EMR values */
+ /* EMR1 & EMR2 */
+ ldr r1, =0x00000000
+ str r1, [r0, #0x88]
+ str r1, [r0, #0x8C]
+
+#ifdef OLD_SDRC_DLLA_CTRL
+ /* SDRC_DLLA_CTRL */
+ ldr r1, =0x00007306
+ str r1, [r0, #0x60]
+
+ ldr r1, =0x00007303
+ str r1, [r0, #0x60]
+#else
+ /* SDRC_DLLA_CTRL */
+ ldr r1, =0x00000506
+ str r1, [r0, #0x60]
+
+ ldr r1, =0x00000503
+ str r1, [r0, #0x60]
+#endif
+
+#ifdef __BROKEN_FEATURE__
+ /* SDRC_DLLB_CTRL */
+ ldr r1, =0x00000506
+ str r1, [r0, #0x68]
+
+ ldr r1, =0x00000503
+ str r1, [r0, #0x68]
+#endif
+
+ /* little delay after init */
+ mov r2, #0x1800
+1:
+ subs r2, r2, #0x1
+ bne 1b
+
+ /* Setup base address */
+ ldr r0, =0x00000000 /* NOR address */
+ ldr r1, =SDRAM_BASE_ADDRESS /* SDRAM address */
+ ldr r2, =0x20000 /* Size: 128KB */
+
+copy_loop:
+ ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r0, r2
+ ble copy_loop
+
+ ldr r1, =SDRAM_BASE_ADDRESS
+ mov lr, pc
+ mov pc, r1
+#endif
+
+prcm_setup:
+ ldr r0, =OMAP2420_CM_BASE
+ ldr r1, [r0, #0x544] /* CLKSEL2_PLL */
+ bic r1, r1, #0x03
+ orr r1, r1, #0x02
+ str r1, [r0, #0x544]
+
+ ldr r1, [r0, #0x500]
+ bic r1, r1, #0x03
+ orr r1, r1, #0x01
+ str r1, [r0, #0x500]
+
+ ldr r1, [r0, #0x140]
+ bic r1, r1, #0x1f
+ orr r1, r1, #0x02
+ str r1, [r0, #0x140]
+
+#ifdef PRCM_CONFIG_I
+ ldr r1, =0x000003C3
+#else
+ ldr r1, =0x00000343
+#endif
+ str r1, [r0, #0x840]
+
+ ldr r1, =0x00000002
+ str r1, [r0, #0x340]
+
+ ldr r1, =CM_CLKSEL1_CORE
+#ifdef PRCM_CONFIG_I
+ ldr r2, =0x08300C44
+#else
+ ldr r2, =0x04600C26
+#endif
+ str r2, [r1]
+
+ ldr r0, =OMAP2420_CM_BASE
+ ldr r1, [r0, #0x084]
+ and r1, r1, #0x01
+ cmp r1, #0x01
+ bne clkvalid
+
+ b .
+
+clkvalid:
+ mov r1, #0x01
+ str r1, [r0, #0x080]
+
+waitvalid:
+ ldr r1, [r0, #0x084]
+ and r1, r1, #0x01
+ cmp r1, #0x00
+ bne waitvalid
+
+ ldr r0, =CM_CLKSEL1_PLL
+#ifdef PRCM_CONFIG_I
+ ldr r1, =0x01837100
+#else
+ ldr r1, =0x01832100
+#endif
+ str r1, [r0]
+
+ ldr r0, =PRCM_CLKCFG_CTRL
+ mov r1, #0x01
+ str r1, [r0]
+ mov r6, #0x50
+loop1:
+ subs r6, r6, #0x01
+ cmp r6, #0x01
+ bne loop1
+
+ ldr r0, =CM_CLKEN_PLL
+ mov r1, #0x0f
+ str r1, [r0]
+
+ mov r6, #0x100
+loop2:
+ subs r6, r6, #0x01
+ cmp r6, #0x01
+ bne loop2
+
+ ldr r0, =0x48008200
+ ldr r1, =0xbfffffff
+ str r1, [r0]
+
+ ldr r0, =0x48008210
+ ldr r1, =0xfffffff9
+ str r1, [r0]
+
+#if 1
+ ldr r0, =0x4806a004
+ ldr r1, =0x00
+ strb r1, [r0]
+
+ ldr r0, =0x4806a020
+ ldr r1, =0x07
+ strb r1, [r0]
+
+ ldr r0, =0x4806a00c
+ ldr r1, =0x83
+ strb r1, [r0]
+
+ ldr r0, =0x4806a000
+ ldr r1, =0x1a
+ strb r1, [r0]
+
+ ldr r0, =0x4806a004
+ ldr r1, =0x00
+ strb r1, [r0]
+
+ ldr r0, =0x4806a00c
+ ldr r1, =0x03
+ strb r1, [r0]
+
+ ldr r0, =0x4806a010
+ ldr r1, =0x03
+ strb r1, [r0]
+
+ ldr r0, =0x4806a008
+ ldr r1, =0x04
+ strb r1, [r0]
+
+ ldr r0, =0x4806a020
+ ldr r1, =0x00
+ strb r1, [r0]
+
+#if 0
+ ldr r0, =0x4806a000
+ mov r1, #'u'
+ strb r1, [r0]
+#endif
+
+#if 0
+ /* LED0 OFF */
+ ldr r3, =0x480000E5
+ mov r4, #0x0b
+ strb r4, [r3]
+#endif
+
+#endif
+
+ ldr sp, SRAM_STACK
+ str ip, [sp] /* stash old link register */
+ mov ip, lr /* save link reg across call */
+ bl s_init /* go setup pll,mux,memory */
+ ldr ip, [sp] /* restore save ip */
+ mov lr, ip /* restore link reg */
+
+ /* map interrupt controller */
+ ldr r0, VAL_INTH_SETUP
+ mcr p15, 0, r0, c15, c2, 4
+
+ /* back to arch calling code */
+ mov pc, lr
+
+ /* the literal pools origin */
+ .ltorg
+
+VAL_INTH_SETUP:
+ .word PERIFERAL_PORT_BASE
+SRAM_STACK:
+ .word LOW_LEVEL_SRAM_STACK
diff --git a/board/apollon/sys_info.c b/board/apollon/sys_info.c
new file mode 100644
index 0000000..1ae4159
--- /dev/null
+++ b/board/apollon/sys_info.c
@@ -0,0 +1,408 @@
+/*
+ * (C) Copyright 2005-2007
+ * Samsung Electronics,
+ * Kyungmin Park <kyungmin.park at samsung.com>
+ *
+ * Derived from omap2420
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/omap2420.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mem.h> /* get mem tables */
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <i2c.h>
+
+/**************************************************************************
+ * get_prod_id() - get id info from chips
+ ***************************************************************************/
+static u32 get_prod_id(void)
+{
+ u32 p;
+ p = __raw_readl(PRODUCTION_ID); /* get production ID */
+ return ((p & CPU_242X_PID_MASK) >> 16);
+}
+
+/**************************************************************************
+ * get_cpu_type() - low level get cpu type
+ * - no C globals yet.
+ * - just looking to say if this is a 2422 or 2420 or ...
+ * - to start with we will look at switch settings..
+ * - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics
+ * (mux for 2420, non-mux for 2422).
+ ***************************************************************************/
+u32 get_cpu_type(void)
+{
+ u32 v;
+
+ switch (get_prod_id()) {
+ case 1:; /* 2420 */
+ case 2:
+ return (CPU_2420);
+ break; /* 2420 pop */
+ case 4:
+ return (CPU_2422);
+ break;
+ case 8:
+ return (CPU_2423);
+ break;
+ default:
+ break; /* early 2420/2422's unmarked */
+ }
+
+ v = __raw_readl(TAP_IDCODE_REG);
+ v &= CPU_24XX_ID_MASK;
+ if (v == CPU_2420_CHIPID) { /* currently 2420 and 2422 have same id */
+ if (is_gpmc_muxed() == GPMC_MUXED) /* if mux'ed */
+ return (CPU_2420);
+ else
+ return (CPU_2422);
+ } else
+ return (CPU_2420); /* don't know, say 2420 */
+}
+
+/******************************************
+ * get_cpu_rev(void) - extract version info
+ ******************************************/
+u32 get_cpu_rev(void)
+{
+ u32 v;
+ v = __raw_readl(TAP_IDCODE_REG);
+ v = v >> 28;
+ return (v + 1); /* currently 2422 and 2420 match up */
+}
+
+/****************************************************
+ * is_mem_sdr() - return 1 if mem type in use is SDR
+ ****************************************************/
+u32 is_mem_sdr(void)
+{
+ volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET);
+ if (*burst == H4_2420_SDRC_MR_0_SDR)
+ return (1);
+ return (0);
+}
+
+/***********************************************************
+ * get_mem_type() - identify type of mDDR part used.
+ * 2422 uses stacked DDR, 2 parts CS0/CS1.
+ * 2420 may have 1 or 2, no good way to know...only init 1...
+ * when eeprom data is up we can select 1 more.
+ *************************************************************/
+u32 get_mem_type(void)
+{
+ u32 cpu, sdr = is_mem_sdr();
+
+ cpu = get_cpu_type();
+ if (cpu == CPU_2422 || cpu == CPU_2423)
+ return (DDR_STACKED);
+
+ if (get_prod_id() == 0x2)
+ return (XDR_POP);
+
+ if (get_board_type() == BOARD_H4_MENELAUS)
+ if (sdr)
+ return (SDR_DISCRETE);
+ else
+ return (DDR_COMBO);
+ else if (sdr) /* SDP + SDR kit */
+ return (SDR_DISCRETE);
+ else
+ return (DDR_DISCRETE); /* origional SDP */
+}
+
+/***********************************************************************
+ * get_cs0_size() - get size of chip select 0/1
+ ************************************************************************/
+u32 get_sdr_cs_size(u32 offset)
+{
+ u32 size;
+ size = __raw_readl(SDRC_MCFG_0 + offset) >> 8; /* get ram size field */
+ size &= 0x2FF; /* remove unwanted bits */
+ size *= SZ_2M; /* find size in MB */
+ return (size);
+}
+
+/***********************************************************************
+ * get_board_type() - get board type based on current production stats.
+ * --- NOTE: 2 I2C EEPROMs will someday be populated with proper info.
+ * when they are available we can get info from there. This should
+ * be correct of all known boards up until today.
+ ************************************************************************/
+u32 get_board_type(void)
+{
+#if 0
+ if (i2c_probe(I2C_MENELAUS) == 0)
+ return (BOARD_H4_MENELAUS);
+ else
+#endif
+ return (BOARD_H4_SDP);
+}
+
+/******************************************************************
+ * get_sysboot_value() - get init word settings (dip switch on h4)
+ ******************************************************************/
+inline u32 get_sysboot_value(void)
+{
+ return (0x00000FFF & __raw_readl(CONTROL_STATUS));
+}
+
+/***************************************************************************
+ * get_gpmc0_base() - Return current address hardware will be
+ * fetching from. The below effectively gives what is correct, its a bit
+ * mis-leading compared to the TRM. For the most general case the mask
+ * needs to be also taken into account this does work in practice.
+ * - for u-boot we currently map:
+ * -- 0 to nothing,
+ * -- 4 to flash
+ * -- 8 to enent
+ * -- c to wifi
+ ****************************************************************************/
+u32 get_gpmc0_base(void)
+{
+ u32 b;
+
+ b = __raw_readl(GPMC_CONFIG7_0);
+ b &= 0x1F; /* keep base [5:0] */
+ b = b << 24; /* ret 0x0b000000 */
+ return (b);
+}
+
+/*****************************************************************
+ * is_gpmc_muxed() - tells if address/data lines are multiplexed
+ *****************************************************************/
+u32 is_gpmc_muxed(void)
+{
+ u32 mux;
+ mux = get_sysboot_value();
+ if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3))
+ return (GPMC_MUXED); /* NAND Boot mode */
+ if (mux & BIT1) /* if mux'ed */
+ return (GPMC_MUXED);
+ else
+ return (GPMC_NONMUXED);
+}
+
+/************************************************************************
+ * get_gpmc0_type() - read sysboot lines to see type of memory attached
+ ************************************************************************/
+u32 get_gpmc0_type(void)
+{
+ u32 type;
+ type = get_sysboot_value();
+ if ((type & (BIT3 | BIT2)) == (BIT3 | BIT2))
+ return (TYPE_NAND);
+ else
+ return (TYPE_NOR);
+}
+
+/*******************************************************************
+ * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
+ *******************************************************************/
+u32 get_gpmc0_width(void)
+{
+ u32 width;
+ width = get_sysboot_value();
+ if ((width & 0xF) == (BIT3 | BIT2))
+ return (WIDTH_8BIT);
+ else
+ return (WIDTH_16BIT);
+}
+
+/*********************************************************************
+ * wait_on_value() - common routine to allow waiting for changes in
+ * volatile regs.
+ *********************************************************************/
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
+{
+ u32 i = 0, val;
+ do {
+ ++i;
+ val = __raw_readl(read_addr) & read_bit_mask;
+ if (val == match_value)
+ return (1);
+ if (i == bound)
+ return (0);
+ } while (1);
+}
+
+/*********************************************************************
+ * display_board_info() - print banner with board info.
+ *********************************************************************/
+void display_board_info(u32 btype)
+{
+ char cpu_2420[] = "2420"; /* cpu type */
+ char cpu_2422[] = "2422";
+ char cpu_2423[] = "2423";
+ char db_men[] = "Menelaus"; /* board type */
+ char db_ip[] = "IP";
+ char mem_sdr[] = "mSDR"; /* memory type */
+ char mem_ddr[] = "mDDR";
+ char t_tst[] = "TST"; /* security level */
+ char t_emu[] = "EMU";
+ char t_hs[] = "HS";
+ char t_gp[] = "GP";
+ char unk[] = "?";
+
+ char *cpu_s, *db_s, *mem_s, *sec_s;
+ u32 cpu, rev, sec;
+
+ rev = get_cpu_rev();
+ cpu = get_cpu_type();
+ sec = get_device_type();
+
+ if (is_mem_sdr())
+ mem_s = mem_sdr;
+ else
+ mem_s = mem_ddr;
+
+ if (cpu == CPU_2423)
+ cpu_s = cpu_2423;
+ else if (cpu == CPU_2422)
+ cpu_s = cpu_2422;
+ else
+ cpu_s = cpu_2420;
+
+ if (btype == BOARD_H4_MENELAUS)
+ db_s = db_men;
+ else
+ db_s = db_ip;
+
+ switch (sec) {
+ case TST_DEVICE:
+ sec_s = t_tst;
+ break;
+ case EMU_DEVICE:
+ sec_s = t_emu;
+ break;
+ case HS_DEVICE:
+ sec_s = t_hs;
+ break;
+ case GP_DEVICE:
+ sec_s = t_gp;
+ break;
+ default:
+ sec_s = unk;
+ }
+
+ printf("OMAP%s-%s revision %d\n", cpu_s, sec_s, rev - 1);
+ printf("Samsung Apollon SDP Base Board + %s \n", mem_s);
+}
+
+/*************************************************************************
+ * get_board_rev() - setup to pass kernel board revision information
+ * 0 = 242x IP platform (first 2xx boards)
+ * 1 = 242x Menelaus platfrom.
+ *************************************************************************/
+u32 get_board_rev(void)
+{
+ u32 rev = 0;
+ u32 btype = get_board_type();
+
+ if (btype == BOARD_H4_MENELAUS) {
+ rev = 1;
+ }
+ return (rev);
+}
+
+/********************************************************
+ * get_base(); get upper addr of current execution
+ *******************************************************/
+u32 get_base(void)
+{
+ u32 val;
+ __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
+ val &= 0xF0000000;
+ val >>= 28;
+ return (val);
+}
+
+/********************************************************
+ * get_base2(); get 2upper addr of current execution
+ *******************************************************/
+u32 get_base2(void)
+{
+ u32 val;
+ __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
+ val &= 0xFF000000;
+ val >>= 24;
+ return (val);
+}
+
+/********************************************************
+ * running_in_flash() - tell if currently running in
+ * flash.
+ *******************************************************/
+u32 running_in_flash(void)
+{
+ if (get_base() < 4)
+ return (1); /* in flash */
+ return (0); /* running in SRAM or SDRAM */
+}
+
+/********************************************************
+ * running_in_sram() - tell if currently running in
+ * sram.
+ *******************************************************/
+u32 running_in_sram(void)
+{
+ if (get_base() == 4)
+ return (1); /* in SRAM */
+ return (0); /* running in FLASH or SDRAM */
+}
+
+/********************************************************
+ * running_in_sdram() - tell if currently running in
+ * flash.
+ *******************************************************/
+u32 running_in_sdram(void)
+{
+ if (get_base() > 4)
+ return (1); /* in sdram */
+ return (0); /* running in SRAM or FLASH */
+}
+
+/*************************************************************
+ * running_from_internal_boot() - am I a signed NOR image.
+ *************************************************************/
+u32 running_from_internal_boot(void)
+{
+ u32 v, base;
+
+ v = get_sysboot_value() & BIT3;
+ base = get_base2();
+ /* if running at mask rom flash address and
+ * sysboot3 says this was an internal boot
+ */
+ if ((base == 0x08) && v)
+ return (1);
+ else
+ return (0);
+}
+
+/*************************************************************
+ * get_device_type(): tell if GP/HS/EMU/TST
+ *************************************************************/
+u32 get_device_type(void)
+{
+ int mode;
+ mode = __raw_readl(CONTROL_STATUS) & (BIT10 | BIT9 | BIT8);
+ return (mode >>= 8);
+}
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