[U-Boot-Users] FIS DTC

Michal Simek Monstr at seznam.cz
Sat Apr 5 19:19:54 CEST 2008


Hi Jon, David and others,

I am working on FIS for Microblaze CPU. I would like to use it. I have one problem.

I download latest DTC version from Jon git server.

Version: DTC 1.1.0-g1577696b

I tryied to convert DTS to DTB for Microblaze CPU. (DTS is below)
#dtc -f -O dtb -b 0 -V 16 system.dts 
DTC: dts->dtb  on file "system.dts"
system.dts:27 syntax error
FATAL ERROR: Couldn't read input tree

I got this error - I don't understand what is wrong. Older DTC version has no problem with it.
This part is no problem - I can use older version of DTC(Version: DTC 1.1.0-g2512a7eb-dirty
).

The second things is around mkimage utility. I want to generate ITB file from ITS description.
Latest DTC compiler has problem with it too. 

Can you tell me which version are you using?
I tryied to complile ITS to ITB with older DTC version and this version don't know about data label in kernel specification.
I had no problem to add (for FDT + kernel version) DTB file but kernel file is not loaded.
Is label data = "/incbin/("./linux.bin")"; OK? linux bin is in the same dirctore where is microblaze.its file.

Latest DTC has problem with ITS too
$ mkimage -f microblaze.its  microblaze.itb
FIT format handling
Trying to execute "dtc -I dts -O dtb -p 500 microblaze.its > microblaze.itb.tmp"
DTC: dts->dtb  on file "microblaze.its"
microblaze.its:5 syntax error
FATAL ERROR: Couldn't read input tree
mkimage: Can't read microblaze.itb.tmp: Invalid argument
$ dtc -v
Version: DTC 1.1.0-g1577696b
[monstr at monstr linux-eu-2.6.24]$ 



# mkimage -f microblaze.its  microblaze.itb
FIT format handling
Trying to execute "dtc -I dts -O dtb -p 500 microblaze.its > microblaze.itb.tmp"
DTC: dts->dtb  on file "microblaze.its"
microblaze.its:5 syntax error
FATAL ERROR: Couldn't read input tree
mkimage: Can't read microblaze.itb.tmp: Invalid argument
# cat -n microblaze.its
     1  /*
     2   * Simple U-boot uImage source file containing a single kernel
     3   */
     4  / {
     5          description = "Simple image with single Linux kernel";
     6          #address-cells = <1>;
     7
     8          images {
     9                  kernel at 1 {
    10                          description = "Vanilla Linux kernel";
    11                          data = /incbin/("./linux.bin");
    12                          type = "kernel";
    13                          arch = "microblaze";
    14                          os = "linux";
    15                          compression = "none";
    16                          load = <20000000>;
    17                          entry = <20000000>;
    18                          hash at 1 {
    19                                  algo = "crc32";
    20                          };
    21                          hash at 2 {
    22                                  algo = "sha1";
    23                          };
    24                  };
    25          };
    26
    27          configurations {
    28                  default = "config at 1";
    29                  config at 1 {
    30                          description = "Boot Linux kernel";
    31                          kernel = "kernel at 1";
    32                  };
    33          };
    34  };

Thanks for help,
Michal Simek
www.monstr.eu








     1  /*
     2   * (C) Copyright 2007-2008 Michal Simek
     3   *
     4   * Michal SIMEK <monstr at monstr.eu>
     5   *
     6   * This program is free software; you can redistribute it and/or
     7   * modify it under the terms of the GNU General Public License as
     8   * published by the Free Software Foundation; either version 2 of
     9   * the License, or (at your option) any later version.
    10   *
    11   * This program is distributed in the hope that it will be useful,
    12   * but WITHOUT ANY WARRANTY; without even the implied warranty of
    13   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
    14   * GNU General Public License for more details.
    15   *
    16   * You should have received a copy of the GNU General Public License
    17   * along with this program; if not, write to the Free Software
    18   * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
    19   * MA 02111-1307 USA
    20   *
    21   * CAUTION: This file is automatically generated by libgen.
    22   * Version: Xilinx EDK 9.2.02 EDK_Jm_SP2.3
    23   * Generate by FDT v1.00.a
    24   */
    25
    26  / {
    27          #address-cells = <1>;
    28          #size-cells = <1>;
    29          compatible = "xlnx,microblaze";
    30          model = "testing";
    31          DDR_SDRAM_32Mx16: memory at 20000000 {
    32                  device_type = "memory";
    33                  reg = < 20000000 4000000 >;
    34          } ;
    35          chosen {
    36                  bootargs = "root=/dev/xsysace/disc0/part2";
    37          } ;
    38          cpus {
    39                  #address-cells = <1>;
    40                  #cpus = <1>;
    41                  #size-cells = <0>;
    42                  cpu at 0 {
    43                          clock-frequency = <2faf080>;
    44                          compatible = "xlnx,microblaze-7.00.a";
    45                          d-cache-baseaddr = <20000000>;
    46                          d-cache-highaddr = <21ffffff>;
    47                          d-cache-line-size = <10>;
    48                          d-cache-size = <4000>;
    49                          device_type = "cpu";
    50                          i-cache-baseaddr = <20000000>;
    51                          i-cache-highaddr = <21ffffff>;
    52                          i-cache-line-size = <10>;
    53                          i-cache-size = <4000>;
    54                          model = "microblaze,7.00.a";
    55                          reg = <0>;
    56                          timebase-frequency = <2faf080>;
    57                          xlnx,addr-tag-bits = <b>;
    58                          xlnx,allow-dcache-wr = <1>;
    59                          xlnx,allow-icache-wr = <1>;
    60                          xlnx,area-optimized = <0>;
    61                          xlnx,cache-byte-size = <4000>;
    62                          xlnx,d-lmb = <1>;
    63                          xlnx,d-opb = <0>;
    64                          xlnx,d-plb = <1>;
    65                          xlnx,data-size = <20>;
    66                          xlnx,dcache-addr-tag = <b>;
    67                          xlnx,dcache-byte-size = <4000>;
    68                          xlnx,dcache-line-len = <4>;
    69                          xlnx,dcache-use-fsl = <1>;
    70                          xlnx,debug-enabled = <1>;
    71                          xlnx,div-zero-exception = <1>;
    72                          xlnx,dopb-bus-exception = <0>;
    73                          xlnx,dynamic-bus-sizing = <1>;
    74                          xlnx,edge-is-positive = <1>;
    75                          xlnx,family = "spartan3e";
    76                          xlnx,fpu-exception = <1>;
    77                          xlnx,fsl-data-size = <20>;
    78                          xlnx,fsl-exception = <0>;
    79                          xlnx,fsl-links = <1>;
    80                          xlnx,i-lmb = <1>;
    81                          xlnx,i-opb = <0>;
    82                          xlnx,i-plb = <1>;
    83                          xlnx,icache-line-len = <4>;
    84                          xlnx,icache-use-fsl = <1>;
    85                          xlnx,ill-opcode-exception = <1>;
    86                          xlnx,instance = "microblaze_0";
    87                          xlnx,interconnect = <1>;
    88                          xlnx,interrupt-is-edge = <0>;
    89                          xlnx,iopb-bus-exception = <0>;
    90                          xlnx,mmu-dtlb-size = <4>;
    91                          xlnx,mmu-itlb-size = <2>;
    92                          xlnx,mmu-tlb-access = <3>;
    93                          xlnx,mmu-zones = <2>;
    94                          xlnx,number-of-pc-brk = <2>;
    95                          xlnx,number-of-rd-addr-brk = <0>;
    96                          xlnx,number-of-wr-addr-brk = <0>;
    97                          xlnx,opcode-0x0-illegal = <1>;
    98                          xlnx,pvr = <2>;
    99                          xlnx,pvr-user1 = <12>;
   100                          xlnx,pvr-user2 = <12345678>;
   101                          xlnx,reset-msr = <0>;
   102                          xlnx,sco = <0>;
   103                          xlnx,unaligned-exceptions = <1>;
   104                          xlnx,use-barrel = <1>;
   105                          xlnx,use-dcache = <1>;
   106                          xlnx,use-div = <1>;
   107                          xlnx,use-extended-fsl-instr = <0>;
   108                          xlnx,use-fpu = <2>;
   109                          xlnx,use-hw-mul = <2>;
   110                          xlnx,use-icache = <1>;
   111                          xlnx,use-mmu = <3>;
   112                          xlnx,use-msr-instr = <1>;
   113                          xlnx,use-pcmp-instr = <1>;
   114                  } ;
   115          } ;
   116          mb_plb: plb at 0 {
   117                  #address-cells = <1>;
   118                  #size-cells = <1>;
   119                  compatible = "xlnx,plb-v46-1.00.a";
   120                  ranges ;
   121                  Buttons_3Bit: gpio at 40800000 {
   122                          compatible = "xlnx,xps-gpio-1.00.a";
   123                          interrupt-parent = <&xps_intc_0>;
   124                          interrupts = < 6 2 >;
   125                          reg = < 40800000 100000 >;
   126                          xlnx,all-inputs = <1>;
   127                          xlnx,all-inputs-2 = <0>;
   128                          xlnx,dout-default = <0>;
   129                          xlnx,dout-default-2 = <0>;
   130                          xlnx,family = "spartan3e";
   131                          xlnx,gpio-width = <3>;
   132                          xlnx,interrupt-present = <1>;
   133                          xlnx,is-bidir = <0>;
   134                          xlnx,is-bidir-2 = <1>;
   135                          xlnx,is-dual = <0>;
   136                          xlnx,tri-default = <ffffffff>;
   137                          xlnx,tri-default-2 = <ffffffff>;
   138                  } ;
   139                  Character_LCD_2x16: gpio at 40900000 {
   140                          compatible = "xlnx,xps-gpio-1.00.a";
   141                          reg = < 40900000 100000 >;
   142                          xlnx,all-inputs = <0>;
   143                          xlnx,all-inputs-2 = <0>;
   144                          xlnx,dout-default = <0>;
   145                          xlnx,dout-default-2 = <0>;
   146                          xlnx,family = "spartan3e";
   147                          xlnx,gpio-width = <7>;
   148                          xlnx,interrupt-present = <0>;
   149                          xlnx,is-bidir = <1>;
   150                          xlnx,is-bidir-2 = <1>;
   151                          xlnx,is-dual = <0>;
   152                          xlnx,tri-default = <ffffffff>;
   153                          xlnx,tri-default-2 = <ffffffff>;
   154                  } ;
   155                  DIP_Switches_4Bit: gpio at 40700000 {
   156                          compatible = "xlnx,xps-gpio-1.00.a";
   157                          interrupt-parent = <&xps_intc_0>;
   158                          interrupts = < 7 2 >;
   159                          reg = < 40700000 100000 >;
   160                          xlnx,all-inputs = <1>;
   161                          xlnx,all-inputs-2 = <0>;
   162                          xlnx,dout-default = <0>;
   163                          xlnx,dout-default-2 = <0>;
   164                          xlnx,family = "spartan3e";
   165                          xlnx,gpio-width = <4>;
   166                          xlnx,interrupt-present = <1>;
   167                          xlnx,is-bidir = <0>;
   168                          xlnx,is-bidir-2 = <1>;
   169                          xlnx,is-dual = <0>;
   170                          xlnx,tri-default = <ffffffff>;
   171                          xlnx,tri-default-2 = <ffffffff>;
   172                  } ;
   173                  Ethernet_MAC: ethernet at 40c00000 {
   174                          compatible = "xlnx,xps-ethernetlite-1.00.a";
   175                          device_type = "network";
   176                          interrupt-parent = <&xps_intc_0>;
   177                          interrupts = < 2 0 >;
   178                          local-mac-address = [ 00 00 00 00 00 00 ];
   179                          reg = < 40c00000 100000 >;
   180                          xlnx,duplex = <1>;
   181                          xlnx,family = "spartan3e";
   182                          xlnx,rx-ping-pong = <0>;
   183                          xlnx,tx-ping-pong = <0>;
   184                  } ;
   185                  LEDs_8Bit: gpio at 40600000 {
   186                          compatible = "xlnx,xps-gpio-1.00.a";
   187                          reg = < 40600000 100000 >;
   188                          xlnx,all-inputs = <0>;
   189                          xlnx,all-inputs-2 = <0>;
   190                          xlnx,dout-default = <0>;
   191                          xlnx,dout-default-2 = <0>;
   192                          xlnx,family = "spartan3e";
   193                          xlnx,gpio-width = <8>;
   194                          xlnx,interrupt-present = <0>;
   195                          xlnx,is-bidir = <0>;
   196                          xlnx,is-bidir-2 = <1>;
   197                          xlnx,is-dual = <0>;
   198                          xlnx,tri-default = <ffffffff>;
   199                          xlnx,tri-default-2 = <ffffffff>;
   200                  } ;
   201                  RS232_DCE: serial at 40200000 {
   202                          compatible = "xlnx,xps-uart16550-1.00.a";
   203                          interrupt-parent = <&xps_intc_0>;
   204                          interrupts = < 4 2 >;
   205                          reg = < 40200000 100000 >;
   206                          xlnx,family = "spartan3e";
   207                          xlnx,has-external-rclk = <0>;
   208                          xlnx,has-external-xin = <0>;
   209                          xlnx,is-a-16550 = <1>;
   210                  } ;
   211                  RS232_DTE: serial at 40100000 {
   212                          compatible = "xlnx,xps-uartlite-1.00.a";
   213                          interrupt-parent = <&xps_intc_0>;
   214                          interrupts = < 3 0 >;
   215                          reg = < 40100000 100000 >;
   216                          xlnx,baudrate = <1c200>;
   217                          xlnx,data-bits = <8>;
   218                          xlnx,family = "spartan3e";
   219                          xlnx,odd-parity = <0>;
   220                          xlnx,use-parity = <0>;
   221                  } ;
   222                  SPI_FLASH: xps-spi at 40a00000 {
   223                          compatible = "xlnx,xps-spi-1.00.a";
   224                          interrupt-parent = <&xps_intc_0>;
   225                          interrupts = < 5 2 >;
   226                          reg = < 40a00000 100000 >;
   227                          xlnx,family = "spartan3e";
   228                          xlnx,fifo-exist = <1>;
   229                          xlnx,num-offchip-ss-bits = <4>;
   230                          xlnx,num-ss-bits = <4>;
   231                          xlnx,sck-ratio = <20>;
   232                  } ;
   233                  debug_module: debug at 40300000 {
   234                          compatible = "xlnx,mdm-1.00.a";
   235                          reg = < 40300000 100000 >;
   236                          xlnx,family = "spartan3e";
   237                          xlnx,interconnect = <1>;
   238                          xlnx,jtag-chain = <2>;
   239                          xlnx,mb-dbg-ports = <1>;
   240                          xlnx,uart-width = <8>;
   241                          xlnx,use-uart = <1>;
   242                          xlnx,write-fsl-ports = <1>;
   243                  } ;
   244                  mpmc at 20000000 {
   245                          #address-cells = <1>;
   246                          #size-cells = <1>;
   247                          compatible = "xlnx,mpmc-3.00.a";
   248                  } ;
   249                  xps_intc_0: interrupt-controller at 40000000 {
   250                          #interrupt-cells = <2>;
   251                          compatible = "xlnx,xps-intc-1.00.a";
   252                          interrupt-controller ;
   253                          reg = < 40000000 100000 >;
   254                          xlnx,num-intr-inputs = <8>;
   255                  } ;
   256                  xps_timer_0: timer at 40400000 {
   257                          compatible = "xlnx,xps-timer-1.00.a";
   258                          interrupt-parent = <&xps_intc_0>;
   259                          interrupts = < 0 2 >;
   260                          reg = < 40400000 100000 >;
   261                          xlnx,count-width = <20>;
   262                          xlnx,family = "spartan3e";
   263                          xlnx,gen0-assert = <1>;
   264                          xlnx,gen1-assert = <1>;
   265                          xlnx,one-timer-only = <0>;
   266                          xlnx,trig0-assert = <1>;
   267                          xlnx,trig1-assert = <1>;
   268                  } ;
   269                  xps_timer_1: timer at 40500000 {
   270                          compatible = "xlnx,xps-timer-1.00.a";
   271                          interrupt-parent = <&xps_intc_0>;
   272                          interrupts = < 1 2 >;
   273                          reg = < 40500000 100000 >;
   274                          xlnx,count-width = <20>;
   275                          xlnx,family = "spartan3e";
   276                          xlnx,gen0-assert = <1>;
   277                          xlnx,gen1-assert = <1>;
   278                          xlnx,one-timer-only = <1>;
   279                          xlnx,trig0-assert = <1>;
   280                          xlnx,trig1-assert = <1>;
   281                  } ;
   282          } ;
   283  }  ;







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