[U-Boot-Users] [PATCH] PPC440 Power Management Registers

[Eugene O'Brien]

Hello Stefan,

Here is an updated patch correcting only the pre-existing power
management register definitions. (I might add that these definitions are
not currently used in the U-Boot source tree either.)

CHANGELOG:

ppc440: Fix power mgt definitions for PPC440

Corrected DCR addresses of PPC440 power management registers.
All AMCC PPC440 processors conform to the same DCR address usage for
these registers.

Signed-off-by: Eugene O'Brien <eugene.obrien at advantechamt.com> 


diff --git a/include/ppc440.h b/include/ppc440.h
index 80dd332..34963c5 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1726,17 +1726,10 @@
 #else
 #define CNTRL_DCR_BASE 0x0b0
 #endif
-#if defined(CONFIG_440GX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+
 #define cpc0_er		(CNTRL_DCR_BASE+0x00)	/* CPM enable
register		*/
 #define cpc0_fr		(CNTRL_DCR_BASE+0x01)	/* CPM force
register		*/
 #define cpc0_sr		(CNTRL_DCR_BASE+0x02)	/* CPM status
register		*/
-#else
-#define cpc0_sr		(CNTRL_DCR_BASE+0x00)	/* CPM status
register		*/
-#define cpc0_er		(CNTRL_DCR_BASE+0x01)	/* CPM enable
register		*/
-#define cpc0_fr		(CNTRL_DCR_BASE+0x02)	/* CPM force
register		*/
-#endif
 
 #define cpc0_sys0	(CNTRL_DCR_BASE+0x30)	/* System configuration
reg 0	*/
 #define cpc0_sys1	(CNTRL_DCR_BASE+0x31)	/* System configuration
reg 1	*/


Regards,
Eugene


-----Original Message-----
From: Stefan Roese [mailto:sr at denx.de] 
Sent: April 8, 2008 7:30 AM
To: u-boot-users at lists.sourceforge.net
Cc: Eugene O'Brien
Subject: Re: [U-Boot-Users] [PATCH] PPC440 Power Management Registers

Hi Eugene,

On Monday 07 April 2008, Eugene O'Brien wrote:
> I had a look at all PPC440 processor manuals from AMCC and see that my
> patch applies to all of them. In other words the #else portion is
never
> used. Therefore I am submitting a patch that cleans up this code quite
> nicely.

Great, thanks.

> Another observation that I made is that the PPC440EPx and PPC440GPx
> require more than 32 bits to control the power management functions.
> Therefore I defined a second set of registers cpc1_er, cpc1_fr,
cpc1_sr
> for these processors. These can be used as placeholders for future
> development.

I would prefer to add those when really needed. Let's try to include
only 
defines that are used. This way the headers don't get "polluted" even
more.

> Let me know if this sounds good to you.

Could you please resend you patch without those new registers? And
please send 
it inline and add a proper Signed-off-by line as described here:

http://www.denx.de/wiki/UBoot/Patches

I suggest to use git-send-email for sending patches.

Best regards,
Stefan

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