[U-Boot-Users] SYNC definition problem

[Yang Ronda]

> -----Original Message-----
> From: Bruce Becky 
> Sent: Monday, April 14, 2008 11:39 AM
> To: Yang Ronda
> Cc: u-boot-users at lists.sourceforge.net
> Subject: Re: [U-Boot-Users] SYNC definition problem
> 
> 
> On Apr 11, 2008, at 5:27 PM, Yang Ronda wrote:
> > Hi,
> >
> > I was trying to turn on I-Cache while u-boot is executing 
> out of Flash 
> > on MPC5121 ADS board, and just found the board refused to 
> boot. After 
> > debug and tried many different ways, we finally found that 
> the root of 
> > the problem is the SYNC macro definition in u-boot 
> > include/ppc_asm.tmpl file. The SYNC was defined as
> >
> > #define SYNC \
> >  sync; \
> >  isync
> 
> The problem isn't the macro definition.  That macro is used 
> all over the place - changing global macros to fix a single 
> problem is not a  
> good idea unless there's something inherently wrong with the macro.   
> Which there isn't, in this case.
> 

We checked with a PowerPC core designer showing him this definition. He
said the safe way to use isync is that always issue a sync operation
after isync. Yes nothing is wrong with this macro, but maybe it will be
better by adding a sync in the end? The core designer said "issue a sync
after isync" is documented somewhere, I couldn't find this document
though.

> >
> > By turning on I-cache on powerpc e300 core, ICE bit of HID0 needs  
> > to be set. Before setting ICE, an isync operation need to be  
> > issued. In the cpu/mpc512x/start.S file, this is done by using a  
> > 'SYNC' statement. But we found we need to add one more sync  
> > operation to guarantee isync is complete.
> 
> You should only need a single isync before writing the ICE bit.  I  
> looked at that file, and everywhere I see a write to the ICE bit,  
> there's no SYNC macro being used. Have you changed the code?  It's  
> likely that something completely different is causing your problem,  
> and the extra sync is masking the problem.
> 

In board config header file, I changed CFG_HID0_INIT and CFG_HID0_FINAL
definition by setting ICE. Then use line 389 to line 397 of
cpu/mpc512x/start.S to enable I-Cache. 
	lis	r3, CFG_HID0_INIT at h
	ori	r3, r3, CFG_HID0_INIT at l
	SYNC
	mtspr	HID0, r3

	lis	r3, CFG_HID0_FINAL at h
	ori	r3, r3, CFG_HID0_FINAL at l
	SYNC
	mtspr	HID0, r3

We are trying to speed up the booting process, so we turn on I-Cache
while the code is still running out of Flash. But interesting thing is
that, if we use icache_enable function, which is called while execution
is out of RAM, we don't need to issue sync after isync. Maybe this is
because the Flash is slower than RAM, so we need a sync after isync to
guarantee isync finished execution?
 

Best Regards,
Ronda