[U-Boot-Users] [PATCH v2] PPC405EX(r) ECC and SDRAM Initialization Clean-ups

[Wolfgang Denk]

In message <1209401636-9846-1-git-send-email-gerickson at nuovations.com> you wrote:
> The primary goal of these changes is to unify some of the low-level
> SDRAM and ECC initialization code for the PPC4xx processors that use a
> common DDR2 SDRAM controller.
> 
> In particular, in the case of the 405EX[r], it must initialize SDRAM
> before a primordial stack is available since OCM doesn't exist and the
> data cache does not work for such a purpose. As a consequence, the ECC
> (and SDRAM) initialization code must be stack-free.

Stefan already asked this... I would also like to understand why the
data cache cannot be used for initial RAM as we do on so many other
systems?

I hesitate to throw away good C code in favour of hard to read,  hard
to maintain assembly, especially if this also breaks with some of the
U-Boot design principles.

> ---
>  board/amcc/kilauea/init.S |   53 +++++++++++--
>  board/amcc/makalu/init.S  |   53 +++++++++++--
>  cpu/ppc4xx/Makefile       |    1 +
>  cpu/ppc4xx/ecc.S          |  195 +++++++++++++++++++++++++++++++++++++++++++++
>  cpu/ppc4xx/sdram.c        |   47 +----------
>  5 files changed, 292 insertions(+), 57 deletions(-)

There are coding style violations: C++ comments, trailing white space,
indentation not consequently by TABs.

Best regards,

Wolfgang Denk

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