[U-Boot-Users] [PATCH] add config options for VSC8601 RGMII PHY - 2nd try

[Andre Schwarz]

The Vitesse VSC8601 RGMII PHY has internal delay for both Rx
and Tx clock lines. They are configured using 2 bits in extended
register 0x17.
Therefore CFG_VSC8601_SKEW_TX and CFG_VSC8601_SKEW_RX have
been introduced with valid values 0-3 giving 0.0, 1.4,1.7 and 2.0ns delay.

Signed-off-by: Andre Schwarz <andre.schwarz at matrix-vision.de>
--



 drivers/net/tsec.c |    6 ++++++
 drivers/net/tsec.h |    3 +++
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 9d22aa3..06250ae 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -1277,6 +1277,12 @@ struct phy_info phy_info_VSC8601 = {
                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 #ifdef CFG_VSC8601_SKEWFIX
               
 {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
+#if defined(CFG_VSC8601_SKEW_TX) && defined(CFG_VSC8601_SKEW_RX)
+                {MIIM_EXT_PAGE_ACCESS,1,NULL},
+#define VSC8101_SKEW    (CFG_VSC8601_SKEW_TX<<14)|(CFG_VSC8601_SKEW_RX<<12)
+                {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL},
+                {MIIM_EXT_PAGE_ACCESS,0,NULL},
+#endif
 #endif
                 {miim_end,}
                  },
diff --git a/drivers/net/tsec.h b/drivers/net/tsec.h
index cfa7d1a..213a809 100644
--- a/drivers/net/tsec.h
+++ b/drivers/net/tsec.h
@@ -112,6 +112,8 @@
 #define MIIM_GBIT_CONTROL    0x9
 #define MIIM_GBIT_CONTROL_INIT    0xe00
 
+#define MIIM_EXT_PAGE_ACCESS    0x1f
+
 /* Broadcom BCM54xx -- taken from linux sungem_phy */
 #define MIIM_BCM54xx_AUXSTATUS            0x19
 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK    0x0700
@@ -163,6 +165,7 @@
 /* Vitesse VSC8601 Extended PHY Control Register 1 */
 #define MIIM_VSC8601_EPHY_CON            0x17
 #define MIIM_VSC8601_EPHY_CON_INIT_SKEW    0x1120
+#define MIIM_VSC8601_SKEW_CTRL        0x1c
 
 /* 88E1011 PHY Status Register */
 #define MIIM_88E1011_PHY_STATUS         0x11


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