[U-Boot-Users] [PATCH]:Enable 2D Engine in SM501!
Ryan CHEN
ryan.chen at st.com
Fri Aug 1 05:11:28 CEST 2008
Hi all,
This patch is part 2 for [PATCH:Enable 2D Engine in SM501]. New macro "CONFIG_SM501_ENABLE_2DENGINE" be included to specify codes what enable SM501 2D engine. The macro need be declared in config header file.
Why does it need to enable 2D engine? The reason is most of framebuffer contents need be moved in VRAM when screen scrolls up. The work be done by software in current U-Boot for SM501. The patch is to enable 2D engine to do it by hardware without CPU interference.
Signed-off-by: Ryan Chen <ryan.chen at st.com>
diff --git a/include/sm501.h b/include/sm501.h
index 3e71dbb..516776f 100644
--- a/include/sm501.h
+++ b/include/sm501.h
@@ -40,6 +40,2213 @@ typedef struct {
unsigned int Value;
} SMI_REGS;
+#ifdef CONFIG_SM501_ENABLE_2DENGINE
+/*
+ *
+ * Definitions for the System Configuration registers.
+ *
+ */
+
+#define SYSTEM_CTRL 0x000000
+#define SYSTEM_CTRL_DPMS 31:30
+#define SYSTEM_CTRL_DPMS_VPHP 0
+#define SYSTEM_CTRL_DPMS_VPHN 1
+#define SYSTEM_CTRL_DPMS_VNHP 2
+#define SYSTEM_CTRL_DPMS_VNHN 3
+#define SYSTEM_CTRL_PCI_BURST 29:29
+#define SYSTEM_CTRL_PCI_BURST_DISABLE 0
+#define SYSTEM_CTRL_PCI_BURST_ENABLE 1
+#define SYSTEM_CTRL_CSC_STATUS 28:28
+#define SYSTEM_CTRL_CSC_STATUS_IDLE 0
+#define SYSTEM_CTRL_CSC_STATUS_BUSY 1
+#define SYSTEM_CTRL_PCI_MASTER 25:25
+#define SYSTEM_CTRL_PCI_MASTER_STOP 0
+#define SYSTEM_CTRL_PCI_MASTER_START 1
+#define SYSTEM_CTRL_LATENCY_TIMER 24:24
+#define SYSTEM_CTRL_LATENCY_TIMER_ENABLE 0
+#define SYSTEM_CTRL_LATENCY_TIMER_DISABLE 1
+#define SYSTEM_CTRL_PANEL_STATUS 23:23
+#define SYSTEM_CTRL_PANEL_STATUS_CURRENT 0
+#define SYSTEM_CTRL_PANEL_STATUS_PENDING 1
+#define SYSTEM_CTRL_VIDEO_STATUS 22:22
+#define SYSTEM_CTRL_VIDEO_STATUS_CURRENT 0
+#define SYSTEM_CTRL_VIDEO_STATUS_PENDING 1
+#define SYSTEM_CTRL_DE_FIFO 20:20
+#define SYSTEM_CTRL_DE_FIFO_NOT_EMPTY 0
+#define SYSTEM_CTRL_DE_FIFO_EMPTY 1
+#define SYSTEM_CTRL_DE_STATUS 19:19
+#define SYSTEM_CTRL_DE_STATUS_IDLE 0
+#define SYSTEM_CTRL_DE_STATUS_BUSY 1
+#define SYSTEM_CTRL_CRT_STATUS 17:17
+#define SYSTEM_CTRL_CRT_STATUS_CURRENT 0
+#define SYSTEM_CTRL_CRT_STATUS_PENDING 1
+#define SYSTEM_CTRL_ZVPORT 16:16
+#define SYSTEM_CTRL_ZVPORT_0 0
+#define SYSTEM_CTRL_ZVPORT_1 1
+#define SYSTEM_CTRL_PCI_BURST_READ 15:15
+#define SYSTEM_CTRL_PCI_BURST_READ_DISABLE 0
+#define SYSTEM_CTRL_PCI_BURST_READ_ENABLE 1
+#define SYSTEM_CTRL_DE_ABORT 13:12
+#define SYSTEM_CTRL_DE_ABORT_NORMAL 0
+#define SYSTEM_CTRL_DE_ABORT_2D_ABORT 3
+#define SYSTEM_CTRL_PCI_SUBSYS_LOCK 11:11
+#define SYSTEM_CTRL_PCI_SUBSYS_LOCK_DISABLE 0
+#define SYSTEM_CTRL_PCI_SUBSYS_LOCK_ENABLE 1
+#define SYSTEM_CTRL_PCI_RETRY 7:7
+#define SYSTEM_CTRL_PCI_RETRY_ENABLE 0
+#define SYSTEM_CTRL_PCI_RETRY_DISABLE 1
+#define SYSTEM_CTRL_PCI_CLOCK_RUN 6:6
+#define SYSTEM_CTRL_PCI_CLOCK_RUN_DISABLE 0
+#define SYSTEM_CTRL_PCI_CLOCK_RUN_ENABLE 1
+#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE 5:4
+#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_1 0
+#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_2 1
+#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_4 2
+#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_8 3
+#define SYSTEM_CTRL_CRT_TRISTATE 2:2
+#define SYSTEM_CTRL_CRT_TRISTATE_DISABLE 0
+#define SYSTEM_CTRL_CRT_TRISTATE_ENABLE 1
+#define SYSTEM_CTRL_INTMEM_TRISTATE 1:1
+#define SYSTEM_CTRL_INTMEM_TRISTATE_DISABLE 0
+#define SYSTEM_CTRL_INTMEM_TRISTATE_ENABLE 1
+#define SYSTEM_CTRL_PANEL_TRISTATE 0:0
+#define SYSTEM_CTRL_PANEL_TRISTATE_DISABLE 0
+#define SYSTEM_CTRL_PANEL_TRISTATE_ENABLE 1
+
+#define CURRENT_POWER_GATE 0x000038
+#define CURRENT_POWER_GATE_AC97_I2S 18:18
+#define CURRENT_POWER_GATE_AC97_I2S_DISABLE 0
+#define CURRENT_POWER_GATE_AC97_I2S_ENABLE 1
+#define CURRENT_POWER_GATE_8051 17:17
+#define CURRENT_POWER_GATE_8051_DISABLE 0
+#define CURRENT_POWER_GATE_8051_ENABLE 1
+#define CURRENT_POWER_GATE_PLL 16:16
+#define CURRENT_POWER_GATE_PLL_DISABLE 0
+#define CURRENT_POWER_GATE_PLL_ENABLE 1
+#define CURRENT_POWER_GATE_OSCILLATOR 15:15
+#define CURRENT_POWER_GATE_OSCILLATOR_DISABLE 0
+#define CURRENT_POWER_GATE_OSCILLATOR_ENABLE 1
+#define CURRENT_POWER_GATE_PLL_RECOVERY 14:13
+#define CURRENT_POWER_GATE_PLL_RECOVERY_32 0
+#define CURRENT_POWER_GATE_PLL_RECOVERY_64 1
+#define CURRENT_POWER_GATE_PLL_RECOVERY_96 2
+#define CURRENT_POWER_GATE_PLL_RECOVERY_128 3
+#define CURRENT_POWER_GATE_USB_SLAVE 12:12
+#define CURRENT_POWER_GATE_USB_SLAVE_DISABLE 0
+#define CURRENT_POWER_GATE_USB_SLAVE_ENABLE 1
+#define CURRENT_POWER_GATE_USB_HOST 11:11
+#define CURRENT_POWER_GATE_USB_HOST_DISABLE 0
+#define CURRENT_POWER_GATE_USB_HOST_ENABLE 1
+#define CURRENT_POWER_GATE_SSP0_SSP1 10:10
+#define CURRENT_POWER_GATE_SSP0_SSP1_DISABLE 0
+#define CURRENT_POWER_GATE_SSP0_SSP1_ENABLE 1
+#define CURRENT_POWER_GATE_UART1 8:8
+#define CURRENT_POWER_GATE_UART1_DISABLE 0
+#define CURRENT_POWER_GATE_UART1_ENABLE 1
+#define CURRENT_POWER_GATE_UART0 7:7
+#define CURRENT_POWER_GATE_UART0_DISABLE 0
+#define CURRENT_POWER_GATE_UART0_ENABLE 1
+#define CURRENT_POWER_GATE_GPIO_PWM_I2C 6:6
+#define CURRENT_POWER_GATE_GPIO_PWM_I2C_DISABLE 0
+#define CURRENT_POWER_GATE_GPIO_PWM_I2C_ENABLE 1
+#define CURRENT_POWER_GATE_ZVPORT 5:5
+#define CURRENT_POWER_GATE_ZVPORT_DISABLE 0
+#define CURRENT_POWER_GATE_ZVPORT_ENABLE 1
+#define CURRENT_POWER_GATE_CSC 4:4
+#define CURRENT_POWER_GATE_CSC_DISABLE 0
+#define CURRENT_POWER_GATE_CSC_ENABLE 1
+#define CURRENT_POWER_GATE_2D 3:3
+#define CURRENT_POWER_GATE_2D_DISABLE 0
+#define CURRENT_POWER_GATE_2D_ENABLE 1
+#define CURRENT_POWER_GATE_DISPLAY 2:2
+#define CURRENT_POWER_GATE_DISPLAY_DISABLE 0
+#define CURRENT_POWER_GATE_DISPLAY_ENABLE 1
+#define CURRENT_POWER_GATE_INTMEM 1:1
+#define CURRENT_POWER_GATE_INTMEM_DISABLE 0
+#define CURRENT_POWER_GATE_INTMEM_ENABLE 1
+#define CURRENT_POWER_GATE_HOST 0:0
+#define CURRENT_POWER_GATE_HOST_DISABLE 0
+#define CURRENT_POWER_GATE_HOST_ENABLE 1
+
+#define CURRENT_POWER_CLOCK 0x00003C
+#define CURRENT_POWER_CLOCK_P1XCLK 31:31
+#define CURRENT_POWER_CLOCK_P1XCLK_ENABLE 1
+#define CURRENT_POWER_CLOCK_P1XCLK_DISABLE 0
+#define CURRENT_POWER_CLOCK_PLLCLK_SELECT 30:30
+#define CURRENT_POWER_CLOCK_PLLCLK_SELECT_ENABLE 1
+#define CURRENT_POWER_CLOCK_PLLCLK_SELECT_DISABLE 0
+#define CURRENT_POWER_CLOCK_P2XCLK_SELECT 29:29
+#define CURRENT_POWER_CLOCK_P2XCLK_SELECT_288 0
+#define CURRENT_POWER_CLOCK_P2XCLK_SELECT_336 1
+#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER 28:27
+#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_1 0
+#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_3 1
+#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_5 2
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT 26:24
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_0 0
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_1 1
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_2 2
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_3 3
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_4 4
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_5 5
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_6 6
+#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_7 7
+#define CURRENT_POWER_CLOCK_V2XCLK_SELECT 20:20
+#define CURRENT_POWER_CLOCK_V2XCLK_SELECT_288 0
+#define CURRENT_POWER_CLOCK_V2XCLK_SELECT_336 1
+#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER 19:19
+#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER_1 0
+#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER_3 1
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT 18:16
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_0 0
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_1 1
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_2 2
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_3 3
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_4 4
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_5 5
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_6 6
+#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_7 7
+#define CURRENT_POWER_CLOCK_MCLK_SELECT 12:12
+#define CURRENT_POWER_CLOCK_MCLK_SELECT_288 0
+#define CURRENT_POWER_CLOCK_MCLK_SELECT_336 1
+#define CURRENT_POWER_CLOCK_MCLK_DIVIDER 11:11
+#define CURRENT_POWER_CLOCK_MCLK_DIVIDER_1 0
+#define CURRENT_POWER_CLOCK_MCLK_DIVIDER_3 1
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT 10:8
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_0 0
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_1 1
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_2 2
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_3 3
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_4 4
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_5 5
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_6 6
+#define CURRENT_POWER_CLOCK_MCLK_SHIFT_7 7
+#define CURRENT_POWER_CLOCK_M2XCLK_SELECT 4:4
+#define CURRENT_POWER_CLOCK_M2XCLK_SELECT_288 0
+#define CURRENT_POWER_CLOCK_M2XCLK_SELECT_336 1
+#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER 3:3
+#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER_1 0
+#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER_3 1
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT 2:0
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_0 0
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_1 1
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_2 2
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_3 3
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_4 4
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_5 5
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_6 6
+#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_7 7
+
+#define POWER_MODE0_GATE 0x000040
+#define POWER_MODE0_GATE_AC97_I2S 18:18
+#define POWER_MODE0_GATE_AC97_I2S_DISABLE 0
+#define POWER_MODE0_GATE_AC97_I2S_ENABLE 1
+#define POWER_MODE0_GATE_8051 17:17
+#define POWER_MODE0_GATE_8051_DISABLE 0
+#define POWER_MODE0_GATE_8051_ENABLE 1
+#define POWER_MODE0_GATE_USB_SLAVE 12:12
+#define POWER_MODE0_GATE_USB_SLAVE_DISABLE 0
+#define POWER_MODE0_GATE_USB_SLAVE_ENABLE 1
+#define POWER_MODE0_GATE_USB_HOST 11:11
+#define POWER_MODE0_GATE_USB_HOST_DISABLE 0
+#define POWER_MODE0_GATE_USB_HOST_ENABLE 1
+#define POWER_MODE0_GATE_SSP0_SSP1 10:10
+#define POWER_MODE0_GATE_SSP0_SSP1_DISABLE 0
+#define POWER_MODE0_GATE_SSP0_SSP1_ENABLE 1
+#define POWER_MODE0_GATE_UART1 8:8
+#define POWER_MODE0_GATE_UART1_DISABLE 0
+#define POWER_MODE0_GATE_UART1_ENABLE 1
+#define POWER_MODE0_GATE_UART0 7:7
+#define POWER_MODE0_GATE_UART0_DISABLE 0
+#define POWER_MODE0_GATE_UART0_ENABLE 1
+#define POWER_MODE0_GATE_GPIO_PWM_I2C 6:6
+#define POWER_MODE0_GATE_GPIO_PWM_I2C_DISABLE 0
+#define POWER_MODE0_GATE_GPIO_PWM_I2C_ENABLE 1
+#define POWER_MODE0_GATE_ZVPORT 5:5
+#define POWER_MODE0_GATE_ZVPORT_DISABLE 0
+#define POWER_MODE0_GATE_ZVPORT_ENABLE 1
+#define POWER_MODE0_GATE_CSC 4:4
+#define POWER_MODE0_GATE_CSC_DISABLE 0
+#define POWER_MODE0_GATE_CSC_ENABLE 1
+#define POWER_MODE0_GATE_2D 3:3
+#define POWER_MODE0_GATE_2D_DISABLE 0
+#define POWER_MODE0_GATE_2D_ENABLE 1
+#define POWER_MODE0_GATE_DISPLAY 2:2
+#define POWER_MODE0_GATE_DISPLAY_DISABLE 0
+#define POWER_MODE0_GATE_DISPLAY_ENABLE 1
+#define POWER_MODE0_GATE_INTMEM 1:1
+#define POWER_MODE0_GATE_INTMEM_DISABLE 0
+#define POWER_MODE0_GATE_INTMEM_ENABLE 1
+#define POWER_MODE0_GATE_HOST 0:0
+#define POWER_MODE0_GATE_HOST_DISABLE 0
+#define POWER_MODE0_GATE_HOST_ENABLE 1
+
+#define POWER_MODE0_CLOCK 0x000044
+#define POWER_MODE0_CLOCK_PLL3_P1XCLK 31:31
+#define POWER_MODE0_CLOCK_PLL3_P1XCLK_ENABLE 1
+#define POWER_MODE0_CLOCK_PLL3_P1XCLK_DISABLE 0
+#define POWER_MODE0_CLOCK_PLL3 30:30
+#define POWER_MODE0_CLOCK_PLL3_ENABLE 1
+#define POWER_MODE0_CLOCK_PLL3_DISABLE 0
+#define POWER_MODE0_CLOCK_P2XCLK_SELECT 29:29
+#define POWER_MODE0_CLOCK_P2XCLK_SELECT_288 0
+#define POWER_MODE0_CLOCK_P2XCLK_SELECT_336 1
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER 28:27
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_1 0
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_3 1
+#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_5 2
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT 26:24
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_0 0
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_1 1
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_2 2
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_3 3
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_4 4
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_5 5
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_6 6
+#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_7 7
+#define POWER_MODE0_CLOCK_V2XCLK_SELECT 20:20
+#define POWER_MODE0_CLOCK_V2XCLK_SELECT_288 0
+#define POWER_MODE0_CLOCK_V2XCLK_SELECT_336 1
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER 19:19
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_1 0
+#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_3 1
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT 18:16
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_0 0
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_1 1
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_2 2
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_3 3
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_4 4
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_5 5
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_6 6
+#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_7 7
+#define POWER_MODE0_CLOCK_MCLK_SELECT 12:12
+#define POWER_MODE0_CLOCK_MCLK_SELECT_288 0
+#define POWER_MODE0_CLOCK_MCLK_SELECT_336 1
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER 11:11
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER_1 0
+#define POWER_MODE0_CLOCK_MCLK_DIVIDER_3 1
+#define POWER_MODE0_CLOCK_MCLK_SHIFT 10:8
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_0 0
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_1 1
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_2 2
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_3 3
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_4 4
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_5 5
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_6 6
+#define POWER_MODE0_CLOCK_MCLK_SHIFT_7 7
+#define POWER_MODE0_CLOCK_M2XCLK_SELECT 4:4
+#define POWER_MODE0_CLOCK_M2XCLK_SELECT_288 0
+#define POWER_MODE0_CLOCK_M2XCLK_SELECT_336 1
+#define POWER_MODE0_CLOCK_M2XCLK_DIVIDER 3:3
+#define POWER_MODE0_CLOCK_M2XCLK_DIVIDER_1 0
+#define POWER_MODE0_CLOCK_M2XCLK_DIVIDER_3 1
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT 2:0
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_0 0
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_1 1
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_2 2
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_3 3
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_4 4
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_5 5
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_6 6
+#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_7 7
+
+#define POWER_MODE1_GATE 0x000048
+#define POWER_MODE1_GATE_AC97_I2S 18:18
+#define POWER_MODE1_GATE_AC97_I2S_DISABLE 0
+#define POWER_MODE1_GATE_AC97_I2S_ENABLE 1
+#define POWER_MODE1_GATE_8051 17:17
+#define POWER_MODE1_GATE_8051_DISABLE 0
+#define POWER_MODE1_GATE_8051_ENABLE 1
+#define POWER_MODE1_GATE_USB_SLAVE 12:12
+#define POWER_MODE1_GATE_USB_SLAVE_DISABLE 0
+#define POWER_MODE1_GATE_USB_SLAVE_ENABLE 1
+#define POWER_MODE1_GATE_USB_HOST 11:11
+#define POWER_MODE1_GATE_USB_HOST_DISABLE 0
+#define POWER_MODE1_GATE_USB_HOST_ENABLE 1
+#define POWER_MODE1_GATE_SSP0_SSP1 10:10
+#define POWER_MODE1_GATE_SSP0_SSP1_DISABLE 0
+#define POWER_MODE1_GATE_SSP0_SSP1_ENABLE 1
+#define POWER_MODE1_GATE_UART1 8:8
+#define POWER_MODE1_GATE_UART1_DISABLE 0
+#define POWER_MODE1_GATE_UART1_ENABLE 1
+#define POWER_MODE1_GATE_UART0 7:7
+#define POWER_MODE1_GATE_UART0_DISABLE 0
+#define POWER_MODE1_GATE_UART0_ENABLE 1
+#define POWER_MODE1_GATE_GPIO_PWM_I2C 6:6
+#define POWER_MODE1_GATE_GPIO_PWM_I2C_DISABLE 0
+#define POWER_MODE1_GATE_GPIO_PWM_I2C_ENABLE 1
+#define POWER_MODE1_GATE_ZVPORT 5:5
+#define POWER_MODE1_GATE_ZVPORT_DISABLE 0
+#define POWER_MODE1_GATE_ZVPORT_ENABLE 1
+#define POWER_MODE1_GATE_CSC 4:4
+#define POWER_MODE1_GATE_CSC_DISABLE 0
+#define POWER_MODE1_GATE_CSC_ENABLE 1
+#define POWER_MODE1_GATE_2D 3:3
+#define POWER_MODE1_GATE_2D_DISABLE 0
+#define POWER_MODE1_GATE_2D_ENABLE 1
+#define POWER_MODE1_GATE_DISPLAY 2:2
+#define POWER_MODE1_GATE_DISPLAY_DISABLE 0
+#define POWER_MODE1_GATE_DISPLAY_ENABLE 1
+#define POWER_MODE1_GATE_INTMEM 1:1
+#define POWER_MODE1_GATE_INTMEM_DISABLE 0
+#define POWER_MODE1_GATE_INTMEM_ENABLE 1
+#define POWER_MODE1_GATE_HOST 0:0
+#define POWER_MODE1_GATE_HOST_DISABLE 0
+#define POWER_MODE1_GATE_HOST_ENABLE 1
+
+#define POWER_MODE1_CLOCK 0x00004C
+#define POWER_MODE1_CLOCK_PLL3_P1XCLK 31:31
+#define POWER_MODE1_CLOCK_PLL3_P1XCLK_ENABLE 1
+#define POWER_MODE1_CLOCK_PLL3_P1XCLK_DISABLE 0
+#define POWER_MODE1_CLOCK_PLL3 30:30
+#define POWER_MODE1_CLOCK_PLL3_ENABLE 1
+#define POWER_MODE1_CLOCK_PLL3_DISABLE 0
+#define POWER_MODE1_CLOCK_P2XCLK_SELECT 29:29
+#define POWER_MODE1_CLOCK_P2XCLK_SELECT_288 0
+#define POWER_MODE1_CLOCK_P2XCLK_SELECT_336 1
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER 28:27
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_1 0
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_3 1
+#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_5 2
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT 26:24
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_0 0
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_1 1
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_2 2
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_3 3
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_4 4
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_5 5
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_6 6
+#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_7 7
+#define POWER_MODE1_CLOCK_V2XCLK_SELECT 20:20
+#define POWER_MODE1_CLOCK_V2XCLK_SELECT_288 0
+#define POWER_MODE1_CLOCK_V2XCLK_SELECT_336 1
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER 19:19
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_1 0
+#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_3 1
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT 18:16
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_0 0
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_1 1
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_2 2
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_3 3
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_4 4
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_5 5
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_6 6
+#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_7 7
+#define POWER_MODE1_CLOCK_MCLK_SELECT 12:12
+#define POWER_MODE1_CLOCK_MCLK_SELECT_288 0
+#define POWER_MODE1_CLOCK_MCLK_SELECT_336 1
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER 11:11
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER_1 0
+#define POWER_MODE1_CLOCK_MCLK_DIVIDER_3 1
+#define POWER_MODE1_CLOCK_MCLK_SHIFT 10:8
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_0 0
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_1 1
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_2 2
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_3 3
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_4 4
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_5 5
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_6 6
+#define POWER_MODE1_CLOCK_MCLK_SHIFT_7 7
+#define POWER_MODE1_CLOCK_M2XCLK_SELECT 4:4
+#define POWER_MODE1_CLOCK_M2XCLK_SELECT_288 0
+#define POWER_MODE1_CLOCK_M2XCLK_SELECT_336 1
+#define POWER_MODE1_CLOCK_M2XCLK_DIVIDER 3:3
+#define POWER_MODE1_CLOCK_M2XCLK_DIVIDER_1 0
+#define POWER_MODE1_CLOCK_M2XCLK_DIVIDER_3 1
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT 2:0
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_0 0
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_1 1
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_2 2
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_3 3
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_4 4
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_5 5
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_6 6
+#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_7 7
+
+#define POWER_SLEEP_GATE 0x000050
+#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK 22:19
+#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_4096 0
+#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_2048 1
+#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_1024 2
+#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_512 3
+#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_256 4
+#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_128 5
+#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_64 6
+#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_32 7
+#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_16 8
+#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_8 9
+#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_4 10
+#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_2 11
+#define POWER_SLEEP_GATE_PLL_RECOVERY 14:13
+#define POWER_SLEEP_GATE_PLL_RECOVERY_32 0
+#define POWER_SLEEP_GATE_PLL_RECOVERY_64 1
+#define POWER_SLEEP_GATE_PLL_RECOVERY_96 2
+#define POWER_SLEEP_GATE_PLL_RECOVERY_128 3
+
+#define POWER_MODE_CTRL 0x000054
+#define POWER_MODE_CTRL_SLEEP_STATUS 2:2
+#define POWER_MODE_CTRL_SLEEP_STATUS_INACTIVE 0
+#define POWER_MODE_CTRL_SLEEP_STATUS_ACTIVE 1
+#define POWER_MODE_CTRL_MODE 1:0
+#define POWER_MODE_CTRL_MODE_MODE0 0
+#define POWER_MODE_CTRL_MODE_MODE1 1
+#define POWER_MODE_CTRL_MODE_SLEEP 2
+
+#define TOP_TO_BOTTOM 0
+#define BOTTOM_TO_TOP 1
+#define RIGHT_TO_LEFT BOTTOM_TO_TOP
+#define LEFT_TO_RIGHT TOP_TO_BOTTOM
+
+// 2D registers.
+#define DE_REGISTER_OFFSET 0x100000
+#define DE_SOURCE 0x000000
+#define DE_SOURCE_WRAP 31:31
+#define DE_SOURCE_WRAP_DISABLE 0
+#define DE_SOURCE_WRAP_ENABLE 1
+#define DE_SOURCE_X_K1 29:16
+#define DE_SOURCE_Y_K2 15:0
+
+#define DE_DESTINATION 0x000004
+#define DE_DESTINATION_WRAP 31:31
+#define DE_DESTINATION_WRAP_DISABLE 0
+#define DE_DESTINATION_WRAP_ENABLE 1
+#define DE_DESTINATION_X 28:16
+#define DE_DESTINATION_Y 15:0
+
+#define DE_DIMENSION 0x000008
+#define DE_DIMENSION_X 28:16
+#define DE_DIMENSION_Y_ET 15:0
+
+#define DE_CONTROL 0x00000C
+#define DE_CONTROL_STATUS 31:31
+#define DE_CONTROL_STATUS_STOP 0
+#define DE_CONTROL_STATUS_START 1
+#define DE_CONTROL_PATTERN 30:30
+#define DE_CONTROL_PATTERN_MONO 0
+#define DE_CONTROL_PATTERN_COLOR 1
+#define DE_CONTROL_UPDATE_DESTINATION_X 29:29
+#define DE_CONTROL_UPDATE_DESTINATION_X_DISABLE 0
+#define DE_CONTROL_UPDATE_DESTINATION_X_ENABLE 1
+#define DE_CONTROL_QUICK_START 28:28
+#define DE_CONTROL_QUICK_START_DISABLE 0
+#define DE_CONTROL_QUICK_START_ENABLE 1
+#define DE_CONTROL_DIRECTION 27:27
+#define DE_CONTROL_DIRECTION_LEFT_TO_RIGHT 0
+#define DE_CONTROL_DIRECTION_RIGHT_TO_LEFT 1
+#define DE_CONTROL_MAJOR 26:26
+#define DE_CONTROL_MAJOR_X 0
+#define DE_CONTROL_MAJOR_Y 1
+#define DE_CONTROL_STEP_X 25:25
+#define DE_CONTROL_STEP_X_POSITIVE 1
+#define DE_CONTROL_STEP_X_NEGATIVE 0
+#define DE_CONTROL_STEP_Y 24:24
+#define DE_CONTROL_STEP_Y_POSITIVE 1
+#define DE_CONTROL_STEP_Y_NEGATIVE 0
+#define DE_CONTROL_STRETCH 23:23
+#define DE_CONTROL_STRETCH_DISABLE 0
+#define DE_CONTROL_STRETCH_ENABLE 1
+#define DE_CONTROL_HOST 22:22
+#define DE_CONTROL_HOST_COLOR 0
+#define DE_CONTROL_HOST_MONO 1
+#define DE_CONTROL_LAST_PIXEL 21:21
+#define DE_CONTROL_LAST_PIXEL_OFF 0
+#define DE_CONTROL_LAST_PIXEL_ON 1
+#define DE_CONTROL_COMMAND 20:16
+#define DE_CONTROL_COMMAND_BITBLT 0
+#define DE_CONTROL_COMMAND_RECTANGLE_FILL 1
+#define DE_CONTROL_COMMAND_DE_TILE 2
+#define DE_CONTROL_COMMAND_TRAPEZOID_FILL 3
+#define DE_CONTROL_COMMAND_ALPHA_BLEND 4
+#define DE_CONTROL_COMMAND_RLE_STRIP 5
+#define DE_CONTROL_COMMAND_SHORT_STROKE 6
+#define DE_CONTROL_COMMAND_LINE_DRAW 7
+#define DE_CONTROL_COMMAND_HOST_WRITE 8
+#define DE_CONTROL_COMMAND_HOST_READ 9
+#define DE_CONTROL_COMMAND_HOST_WRITE_BOTTOM_UP 10
+#define DE_CONTROL_COMMAND_ROTATE 11
+#define DE_CONTROL_COMMAND_FONT 12
+#define DE_CONTROL_COMMAND_TEXTURE_LOAD 15
+#define DE_CONTROL_ROP_SELECT 15:15
+#define DE_CONTROL_ROP_SELECT_ROP3 0
+#define DE_CONTROL_ROP_SELECT_ROP2 1
+#define DE_CONTROL_ROP2_SOURCE 14:14
+#define DE_CONTROL_ROP2_SOURCE_BITMAP 0
+#define DE_CONTROL_ROP2_SOURCE_PATTERN 1
+#define DE_CONTROL_MONO_DATA 13:12
+#define DE_CONTROL_MONO_DATA_NOT_PACKED 0
+#define DE_CONTROL_MONO_DATA_8_PACKED 1
+#define DE_CONTROL_MONO_DATA_16_PACKED 2
+#define DE_CONTROL_MONO_DATA_32_PACKED 3
+#define DE_CONTROL_REPEAT_ROTATE 11:11
+#define DE_CONTROL_REPEAT_ROTATE_DISABLE 0
+#define DE_CONTROL_REPEAT_ROTATE_ENABLE 1
+#define DE_CONTROL_TRANSPARENCY_MATCH 10:10
+#define DE_CONTROL_TRANSPARENCY_MATCH_OPAQUE 0
+#define DE_CONTROL_TRANSPARENCY_MATCH_TRANSPARENT 1
+#define DE_CONTROL_TRANSPARENCY_SELECT 9:9
+#define DE_CONTROL_TRANSPARENCY_SELECT_SOURCE 0
+#define DE_CONTROL_TRANSPARENCY_SELECT_DESTINATION 1
+#define DE_CONTROL_TRANSPARENCY 8:8
+#define DE_CONTROL_TRANSPARENCY_DISABLE 0
+#define DE_CONTROL_TRANSPARENCY_ENABLE 1
+#define DE_CONTROL_ROP 7:0
+
+// Pseudo fields.
+
+#define DE_CONTROL_SHORT_STROKE_DIR 27:24
+#define DE_CONTROL_SHORT_STROKE_DIR_225 0
+#define DE_CONTROL_SHORT_STROKE_DIR_135 1
+#define DE_CONTROL_SHORT_STROKE_DIR_315 2
+#define DE_CONTROL_SHORT_STROKE_DIR_45 3
+#define DE_CONTROL_SHORT_STROKE_DIR_270 4
+#define DE_CONTROL_SHORT_STROKE_DIR_90 5
+#define DE_CONTROL_SHORT_STROKE_DIR_180 8
+#define DE_CONTROL_SHORT_STROKE_DIR_0 10
+#define DE_CONTROL_ROTATION 25:24
+#define DE_CONTROL_ROTATION_0 0
+#define DE_CONTROL_ROTATION_270 1
+#define DE_CONTROL_ROTATION_90 2
+#define DE_CONTROL_ROTATION_180 3
+
+#define DE_PITCH 0x000010
+#define DE_PITCH_DESTINATION 28:16
+#define DE_PITCH_SOURCE 12:0
+
+#define DE_FOREGROUND 0x000014
+#define DE_FOREGROUND_COLOR 31:0
+
+#define DE_BACKGROUND 0x000018
+#define DE_BACKGROUND_COLOR 31:0
+
+#define DE_STRETCH_FORMAT 0x00001C
+#define DE_STRETCH_FORMAT_PATTERN_XY 30:30
+#define DE_STRETCH_FORMAT_PATTERN_XY_NORMAL 0
+#define DE_STRETCH_FORMAT_PATTERN_XY_OVERWRITE 1
+#define DE_STRETCH_FORMAT_PATTERN_Y 29:27
+#define DE_STRETCH_FORMAT_PATTERN_X 25:23
+#define DE_STRETCH_FORMAT_PIXEL_FORMAT 21:20
+#define DE_STRETCH_FORMAT_PIXEL_FORMAT_8 0
+#define DE_STRETCH_FORMAT_PIXEL_FORMAT_16 1
+#define DE_STRETCH_FORMAT_PIXEL_FORMAT_32 2
+#define DE_STRETCH_FORMAT_ADDRESSING 19:16
+#define DE_STRETCH_FORMAT_ADDRESSING_XY 0
+#define DE_STRETCH_FORMAT_ADDRESSING_LINEAR 15
+#define DE_STRETCH_FORMAT_SOURCE_HEIGHT 11:0
+
+#define DE_COLOR_COMPARE 0x000020
+#define DE_COLOR_COMPARE_COLOR 23:0
+
+#define DE_COLOR_COMPARE_MASK 0x000024
+#define DE_COLOR_COMPARE_MASK_MASKS 23:0
+
+#define DE_MASKS 0x000028
+#define DE_MASKS_BYTE_MASK 31:16
+#define DE_MASKS_BIT_MASK 15:0
+
+#define DE_CLIP_TL 0x00002C
+#define DE_CLIP_TL_TOP 31:16
+#define DE_CLIP_TL_STATUS 13:13
+#define DE_CLIP_TL_STATUS_DISABLE 0
+#define DE_CLIP_TL_STATUS_ENABLE 1
+#define DE_CLIP_TL_INHIBIT 12:12
+#define DE_CLIP_TL_INHIBIT_OUTSIDE 0
+#define DE_CLIP_TL_INHIBIT_INSIDE 1
+#define DE_CLIP_TL_LEFT 11:0
+
+#define DE_CLIP_BR 0x000030
+#define DE_CLIP_BR_BOTTOM 31:16
+#define DE_CLIP_BR_RIGHT 12:0
+
+#define DE_MONO_PATTERN_LOW 0x000034
+#define DE_MONO_PATTERN_LOW_PATTERN 31:0
+
+#define DE_MONO_PATTERN_HIGH 0x000038
+#define DE_MONO_PATTERN_HIGH_PATTERN 31:0
+
+#define DE_WINDOW_WIDTH 0x00003C
+#define DE_WINDOW_WIDTH_DESTINATION 28:16
+#define DE_WINDOW_WIDTH_SOURCE 12:0
+
+#define DE_WINDOW_SOURCE_BASE 0x000040
+#define DE_WINDOW_SOURCE_BASE_EXT 27:27
+#define DE_WINDOW_SOURCE_BASE_EXT_LOCAL 0
+#define DE_WINDOW_SOURCE_BASE_EXT_EXTERNAL 1
+#define DE_WINDOW_SOURCE_BASE_CS 26:26
+#define DE_WINDOW_SOURCE_BASE_CS_0 0
+#define DE_WINDOW_SOURCE_BASE_CS_1 1
+#define DE_WINDOW_SOURCE_BASE_ADDRESS 25:0
+
+#define DE_WINDOW_DESTINATION_BASE 0x000044
+#define DE_WINDOW_DESTINATION_BASE_EXT 27:27
+#define DE_WINDOW_DESTINATION_BASE_EXT_LOCAL 0
+#define DE_WINDOW_DESTINATION_BASE_EXT_EXTERNAL 1
+#define DE_WINDOW_DESTINATION_BASE_CS 26:26
+#define DE_WINDOW_DESTINATION_BASE_CS_0 0
+#define DE_WINDOW_DESTINATION_BASE_CS_1 1
+#define DE_WINDOW_DESTINATION_BASE_ADDRESS 25:0
+
+#define DE_ALPHA 0x000048
+#define DE_ALPHA_VALUE 7:0
+
+#define DE_WRAP 0x00004C
+#define DE_WRAP_X 31:16
+#define DE_WRAP_Y 15:0
+
+#define DE_STATUS 0x000050
+#define DE_STATUS_CSC 1:1
+#define DE_STATUS_CSC_CLEAR 0
+#define DE_STATUS_CSC_NOT_ACTIVE 0
+#define DE_STATUS_CSC_ACTIVE 1
+#define DE_STATUS_2D 0:0
+#define DE_STATUS_2D_CLEAR 0
+#define DE_STATUS_2D_NOT_ACTIVE 0
+#define DE_STATUS_2D_ACTIVE 1
+#endif/* CONFIG_SM501_ENABLE_2DENGINE */
+
/* Board specific functions */
unsigned int board_video_init (void);
void board_validate_screen (unsigned int base);
Best Regards,
Ryan Chen
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