[U-Boot] [PATCH 09/14] FSL DDR: Convert MPC8540ADS to new DDR code.

Kumar Gala galak at kernel.crashing.org
Tue Aug 12 18:06:17 CEST 2008


Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
---
 board/freescale/mpc8540ads/Makefile     |   13 +-
 board/freescale/mpc8540ads/ddr.c        |  296 +++++++++++++++++++++++++++++++
 board/freescale/mpc8540ads/mpc8540ads.c |   16 ++-
 include/configs/MPC8540ADS.h            |   70 +++++---
 4 files changed, 360 insertions(+), 35 deletions(-)
 create mode 100644 board/freescale/mpc8540ads/ddr.c

diff --git a/board/freescale/mpc8540ads/Makefile b/board/freescale/mpc8540ads/Makefile
index 2d71cbc..4c6da4d 100644
--- a/board/freescale/mpc8540ads/Makefile
+++ b/board/freescale/mpc8540ads/Makefile
@@ -25,11 +25,14 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o law.o tlb.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS)
diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c
new file mode 100644
index 0000000..1414da9
--- /dev/null
+++ b/board/freescale/mpc8540ads/ddr.c
@@ -0,0 +1,296 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <../cpu/mpc8xxx/fsl_ddr_sdram.h>
+
+#define SDRAM_TYPE_DDR1    2
+#define SDRAM_TYPE_DDR2    3
+#define SDRAM_TYPE_LPDDR1  6
+#define SDRAM_TYPE_DDR3    7
+
+
+static void
+get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
+}
+
+
+unsigned int
+fsl_ddr_sdram_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+
+void
+fsl_ddr_sdram_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0) {
+			i2c_address = SPD_EEPROM_ADDRESS1;
+		}
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+
+void
+fsl_ddr_sdram_dump_memctl_regs(unsigned int ctrl_num)
+{
+	unsigned int i;
+	volatile ccsr_ddr_t *ddr;
+
+	if (ctrl_num == 0)
+		ddr = (void *)CFG_MPC85xx_DDR_ADDR;
+	else
+		ddr = (void *)CFG_MPC85xx_DDR2_ADDR;
+
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		unsigned int bnds = 0;
+		unsigned int config = 0;
+		unsigned int config_2 = 0;
+		unsigned int *pbnds = NULL;
+		unsigned int *pconfig = NULL;
+		unsigned int *pconfig_2 = NULL;
+
+		if (i == 0) {
+			bnds     = ddr->cs0_bnds;
+			config   = ddr->cs0_config;
+			config_2 = ddr->cs0_config_2;
+			pbnds    = (unsigned int *)&ddr->cs0_bnds;
+			pconfig  = (unsigned int *)&ddr->cs0_config;
+			pconfig_2= (unsigned int *)&ddr->cs0_config_2;
+
+		} else if (i == 1) {
+			bnds     = ddr->cs1_bnds;
+			config   = ddr->cs1_config;
+			config_2 = ddr->cs1_config_2;
+			pbnds    = (unsigned int *)&ddr->cs1_bnds;
+			pconfig  = (unsigned int *)&ddr->cs1_config;
+			pconfig_2= (unsigned int *)&ddr->cs1_config_2;
+
+		} else if (i == 2) {
+			bnds     = ddr->cs2_bnds;
+			config   = ddr->cs2_config;
+			config_2 = ddr->cs2_config_2;
+			pbnds    = (unsigned int *)&ddr->cs2_bnds;
+			pconfig  = (unsigned int *)&ddr->cs2_config;
+			pconfig_2= (unsigned int *)&ddr->cs2_config_2;
+
+		} else if (i == 3) {
+			bnds     = ddr->cs3_bnds;
+			config   = ddr->cs3_config;
+			config_2 = ddr->cs3_config_2;
+			pbnds    = (unsigned int *) &ddr->cs3_bnds;
+			pconfig  = (unsigned int *) &ddr->cs3_config;
+			pconfig_2= (unsigned int *) &ddr->cs3_config_2;
+
+		} else {
+			/*
+			 * FIXME what happens if CONFIG_CHIP_SELECTS_PER_CTRL > 4
+			 */
+		}
+
+		printf("cs%u_bnds           = %08X\t%p\n", i, bnds, pbnds);
+		printf("cs%u_config         = %08X\t%p\n", i, config, pconfig);
+		printf("cs%u_config_2       = %08X\t%p\n",
+		       i, config_2, pconfig_2);
+	}
+
+	/*
+	 * Due to inconsistencies between immap_85xx.h and immap_86xx.h,
+	 * you will have to modify the structure member names by hand
+	 * between architectures.
+	 */
+	printf("timing_cfg_3       = %08X\t%p\n",
+	       ddr->timing_cfg_3, &ddr->timing_cfg_3);
+	printf("timing_cfg_0       = %08X\t%p\n",
+	       ddr->timing_cfg_0, &ddr->timing_cfg_0);
+	printf("timing_cfg_1       = %08X\t%p\n",
+	       ddr->timing_cfg_1, &ddr->timing_cfg_1);
+	printf("timing_cfg_2       = %08X\t%p\n",
+	       ddr->timing_cfg_2, &ddr->timing_cfg_2);
+	printf("ddr_sdram_cfg      = %08X\t%p\n",
+	       ddr->sdram_cfg, &ddr->sdram_cfg);
+	printf("ddr_sdram_cfg_2    = %08X\t%p\n",
+	       ddr->sdram_cfg_2, &ddr->sdram_cfg_2);
+	printf("ddr_sdram_mode     = %08X\t%p\n",
+		ddr->sdram_mode, &ddr->sdram_mode);
+	printf("ddr_sdram_mode_2   = %08X\t%p\n",
+		ddr->sdram_mode_2, &ddr->sdram_mode_2);
+	printf("ddr_sdram_interval = %08X\t%p\n",
+		ddr->sdram_interval, &ddr->sdram_interval);
+	printf("ddr_data_init      = %08X\t%p\n",
+		ddr->sdram_data_init, &ddr->sdram_data_init);
+	printf("ddr_sdram_clk_cntl = %08X\t%p\n",
+		ddr->sdram_clk_cntl, &ddr->sdram_clk_cntl);
+	printf("ddr_init_addr      = %08X\t%p\n",
+		ddr->init_addr, &ddr->init_addr);
+	printf("ddr_init_ext_addr  = %08X\t%p\n",
+		ddr->init_ext_addr, &ddr->init_ext_addr);
+
+	printf("timing_cfg_4       = %08X\t%p\n",
+		ddr->timing_cfg_4, &ddr->timing_cfg_4);
+	printf("timing_cfg_5       = %08X\t%p\n",
+		ddr->timing_cfg_5, &ddr->timing_cfg_5);
+	printf("ddr_zq_cntl        = %08X\t%p\n",
+		ddr->ddr_zq_cntl, &ddr->ddr_zq_cntl);
+	printf("ddr_wrlvl_cntl     = %08X\t%p\n",
+		ddr->ddr_wrlvl_cntl, &ddr->ddr_wrlvl_cntl);
+	printf("ddr_pd_cntl        = %08X\t%p\n",
+		ddr->ddr_pd_cntl, &ddr->ddr_pd_cntl);
+	printf("ddr_sr_cntr        = %08X\t%p\n",
+		ddr->ddr_sr_cntr, &ddr->ddr_sr_cntr);
+	printf("ddr_sdram_rcw_1    = %08X\t%p\n",
+		ddr->ddr_sdram_rcw_1, &ddr->ddr_sdram_rcw_1);
+	printf("ddr_sdram_rcw_2    = %08X\t%p\n",
+		ddr->ddr_sdram_rcw_2, &ddr->ddr_sdram_rcw_2);
+
+	printf("debug_1            = %08X\t%p\n",
+	       ddr->debug_1, &ddr->debug_1);
+}
+
+
+void
+fsl_ddr_sdram_set_memctl_regs(const fsl_memctl_config_regs_t *regs,
+			      unsigned int ctrl_num)
+{
+	unsigned int i;
+	volatile ccsr_ddr_t *ddr;
+
+	switch (ctrl_num) {
+	case 0:
+		ddr = (void *)CFG_MPC85xx_DDR_ADDR;
+		break;
+	case 1:
+		ddr = (void *)CFG_MPC85xx_DDR2_ADDR;
+		break;
+	default:
+		printf("fsl_ddr_sdram_set_memctl_regs() unexpected ctrl_num = %u\n", ctrl_num);
+		return;
+	}
+
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (i == 0) {
+			ddr->cs0_bnds = regs->cs[i].bnds;
+			ddr->cs0_config = regs->cs[i].config;
+			ddr->cs0_config_2 = regs->cs[i].config_2;
+
+		} else if (i == 1) {
+			ddr->cs1_bnds = regs->cs[i].bnds;
+			ddr->cs1_config = regs->cs[i].config;
+			ddr->cs1_config_2 = regs->cs[i].config_2;
+
+		} else if (i == 2) {
+			ddr->cs2_bnds = regs->cs[i].bnds;
+			ddr->cs2_config = regs->cs[i].config;
+			ddr->cs2_config_2 = regs->cs[i].config_2;
+
+		} else if (i == 3) {
+			ddr->cs3_bnds = regs->cs[i].bnds;
+			ddr->cs3_config = regs->cs[i].config;
+			ddr->cs3_config_2 = regs->cs[i].config_2;
+		}
+	}
+
+	/*
+	 * Someone decided to use different names from the documentation...
+	 */
+	ddr->timing_cfg_3       = regs->timing_cfg_3;
+	ddr->timing_cfg_1       = regs->timing_cfg_1;
+	ddr->timing_cfg_2       = regs->timing_cfg_2;
+	ddr->sdram_cfg_2        = regs->ddr_sdram_cfg_2;
+	ddr->sdram_mode         = regs->ddr_sdram_mode;
+	ddr->sdram_mode_2       = regs->ddr_sdram_mode_2;
+	ddr->sdram_interval     = regs->ddr_sdram_interval;
+	ddr->sdram_data_init    = regs->ddr_data_init;
+	ddr->sdram_clk_cntl     = regs->ddr_sdram_clk_cntl;
+	ddr->init_addr          = regs->ddr_init_addr;
+	ddr->init_ext_addr      = regs->ddr_init_ext_addr;
+
+	/*
+	 * FIXME: ECC?  Need to program err_disable, err_sbe, and err_int_en
+	 */
+
+	/*
+	 * 200 painful micro-seconds must elapse between
+	 * the DDR clock setup and the DDR config enable.
+	 */
+	udelay(200);
+	asm volatile("sync;isync");
+
+	ddr->sdram_cfg = regs->ddr_sdram_cfg;
+
+	asm("sync;isync;msync");
+	udelay(500);
+}
+
+
+unsigned int
+fsl_ddr_sdram_type_function(void)
+{
+	return SDRAM_TYPE_DDR1;
+}
+
+
+/*
+ * Technically, the memory controller on this part doesn't even
+ * have the clk_adjust field for lack of the SDRAM_CLK_CNTL register.
+ */
+
+unsigned int
+fsl_ddr_sdram_clk_adjust_function(void)
+{
+	return 0;
+}
+
+
+unsigned int
+fsl_ddr_sdram_cpo_override_function(void)
+{
+	return 0;	/* Should be 0 for DDR1 */
+}
+
+
+/*
+ * factors to consider for write data delay:
+ * 	- number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1   clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+
+unsigned int
+fsl_ddr_sdram_write_data_delay_function(void)
+{
+	return 3;
+}
+
+
+/*
+ * factors to consider for half-strength driver enable:
+ * 	- number of DIMMs installed
+ */
+
+unsigned int
+fsl_ddr_sdram_half_strength_driver_enable_function(void)
+{
+	return 0;
+}
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
index 4f068cc..926d9a6 100644
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -28,11 +28,13 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/processor.h>
+#include <asm/mmu.h>
 #include <asm/immap_85xx.h>
-#include <spd_sdram.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 
+#include "../cpu/mpc8xxx/fsl_ddr_sdram.h"
+
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
@@ -82,10 +84,16 @@ initdram(int board_type)
 	}
 #endif
 
-#if defined(CONFIG_SPD_EEPROM)
-	dram_size = spd_sdram ();
+#ifdef CONFIG_SPD_EEPROM
+	dram_size = fsl_ddr_sdram();
+	printf("dram_size = %u\n", dram_size);
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	printf("dram_size = %u after setup_ddr_tlbs\n", dram_size);
+
+	dram_size *= 0x100000;
 #else
-	dram_size = fixed_sdram ();
+	dram_size = fixed_sdram();
 #endif
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index d1d3cc3..cc69c19 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -48,13 +48,6 @@
 #define CONFIG_PCI
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
-
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
-#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
-
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
 /*
@@ -104,28 +97,53 @@
 /*
  * DDR Setup
  */
+#define CONFIG_FSL_DDR1
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#undef CONFIG_FSL_DDR_INTERACTIVE
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 
-#if defined(CONFIG_SPD_EEPROM)
-    /*
-     * Determine DDR configuration from I2C interface.
-     */
-    #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+/*
+ * Number of memory controllers on device
+ */
+#define CONFIG_NUM_DDR_CONTROLLERS	1
 
-#else
-    /*
-     * Manually set up DDR parameters
-     */
-    #define CFG_SDRAM_SIZE	128		/* DDR is 128MB */
-    #define CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
-    #define CFG_DDR_CS0_CONFIG	0x80000002
-    #define CFG_DDR_TIMING_1	0x37344321
-    #define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
-    #define CFG_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
-    #define CFG_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
-    #define CFG_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
-#endif
+/*
+ * Number of DIMM slots per memory controller
+ */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+
+/*
+ * Number of chip selects per memory controller
+ *
+ * The MPC8540 (the chip) has 4 chip selects per memory controller.
+ * However, the MPC8540ADS (the board) has only 1 DIMM slot per memory
+ * controller, so therefore it only has 2 chip selects per memory
+ * controller that are actually connected.
+ */
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/*
+ * I2C addresses of SPD EEPROMs
+ */
+#define SPD_EEPROM_ADDRESS1	0x51	/* CTLR 0 DIMM 0 */
+
+
+/*
+ * These are used when DDR doesn't use SPD.
+ */
+#define CFG_SDRAM_SIZE	128		/* DDR is 128MB */
+#define CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
+#define CFG_DDR_CS0_CONFIG	0x80000002
+#define CFG_DDR_TIMING_1	0x37344321
+#define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CFG_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
+#define CFG_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
+#define CFG_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
 
 
 /*
-- 
1.5.5.1




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