[U-Boot] [PATCH v3 09/16] FSL DDR: Convert MPC8610HPCD to new DDR code.
Kumar Gala
galak at kernel.crashing.org
Thu Aug 21 01:22:51 CEST 2008
From: Jon Loeliger <jdl at freescale.com>
Signed-off-by: Jon Loeliger <jdl at freescale.com>
Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
---
board/freescale/mpc8610hpcd/Makefile | 10 +-
board/freescale/mpc8610hpcd/ddr.c | 223 +++++++++++++++++++++++++++++
board/freescale/mpc8610hpcd/mpc8610hpcd.c | 3 +-
include/configs/MPC8610HPCD.h | 50 +++++--
4 files changed, 264 insertions(+), 22 deletions(-)
create mode 100644 board/freescale/mpc8610hpcd/ddr.c
diff --git a/board/freescale/mpc8610hpcd/Makefile b/board/freescale/mpc8610hpcd/Makefile
index a457c32..dc97c33 100644
--- a/board/freescale/mpc8610hpcd/Makefile
+++ b/board/freescale/mpc8610hpcd/Makefile
@@ -23,14 +23,14 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o law.o
+COBJS-y += $(BOARD).o
+COBJS-y += ddr.o
+COBJS-y += law.o
COBJS-${CONFIG_FSL_DIU_FB} += mpc8610hpcd_diu.o
-COBJS += ${COBJS-y}
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c
new file mode 100644
index 0000000..fca2918
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/ddr.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <../cpu/mpc8xxx/fsl_ddr_sdram.h>
+
+#define SDRAM_TYPE_DDR1 2
+#define SDRAM_TYPE_DDR2 3
+#define SDRAM_TYPE_LPDDR1 6
+#define SDRAM_TYPE_DDR3 7
+
+static void
+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+ i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+ return get_bus_freq(0);
+}
+
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+ unsigned int i2c_address = 0;
+
+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+ if (ctrl_num == 0 && i == 0) {
+ i2c_address = SPD_EEPROM_ADDRESS1;
+ }
+ get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+ }
+}
+
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
+#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
+#endif
+
+void fsl_ddr_dump_memctl_regs(unsigned int ctrl_num)
+{
+ unsigned int i;
+ volatile ccsr_ddr_t *ddr;
+
+ if (ctrl_num == 0)
+ ddr = (void *)CFG_MPC86xx_DDR_ADDR;
+ else
+ ddr = (void *)CFG_MPC86xx_DDR2_ADDR;
+
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ unsigned int bnds = 0;
+ unsigned int config = 0;
+
+ if (i == 0) {
+ bnds = ddr->cs0_bnds;
+ config = ddr->cs0_config;
+
+ } else if (i == 1) {
+ bnds = ddr->cs1_bnds;
+ config = ddr->cs1_config;
+
+ } else if (i == 2) {
+ bnds = ddr->cs2_bnds;
+ config = ddr->cs2_config;
+
+ } else {
+ bnds = ddr->cs3_bnds;
+ config = ddr->cs3_config;
+
+ }
+
+ printf("cs%u_bnds = %08X\n", i, bnds);
+ printf("cs%u_config = %08X\n", i, config);
+ }
+
+ printf("timing_cfg_3 = %08X\n", ddr->timing_cfg_3);
+ printf("timing_cfg_0 = %08X\n", ddr->timing_cfg_0);
+ printf("timing_cfg_1 = %08X\n", ddr->timing_cfg_1);
+ printf("timing_cfg_2 = %08X\n", ddr->timing_cfg_2);
+ printf("ddr_sdram_cfg = %08X\n", ddr->sdram_cfg_1);
+ printf("ddr_sdram_cfg_2 = %08X\n", ddr->sdram_cfg_2);
+ printf("ddr_sdram_mode = %08X\n", ddr->sdram_mode_1);
+ printf("ddr_sdram_mode_2 = %08X\n", ddr->sdram_mode_2);
+ printf("ddr_sdram_interval = %08X\n", ddr->sdram_interval);
+ printf("ddr_data_init = %08X\n", ddr->sdram_data_init);
+ printf("ddr_sdram_clk_cntl = %08X\n", ddr->sdram_clk_cntl);
+ printf("ddr_init_addr = %08X\n", ddr->init_addr);
+}
+
+void fsl_ddr_set_memctl_regs(const fsl_memctl_config_regs_t *regs,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+ volatile ccsr_ddr_t *ddr;
+
+ switch (ctrl_num) {
+ case 0:
+ ddr = (void *)CFG_MPC86xx_DDR_ADDR;
+ break;
+ case 1:
+ ddr = (void *)CFG_MPC86xx_DDR2_ADDR;
+ break;
+ default:
+ printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+ return;
+ }
+
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (i == 0) {
+ ddr->cs0_bnds = regs->cs[i].bnds;
+ ddr->cs0_config = regs->cs[i].config;
+
+ } else if (i == 1) {
+ ddr->cs1_bnds = regs->cs[i].bnds;
+ ddr->cs1_config = regs->cs[i].config;
+
+ } else if (i == 2) {
+ ddr->cs2_bnds = regs->cs[i].bnds;
+ ddr->cs2_config = regs->cs[i].config;
+
+ } else if (i == 3) {
+ ddr->cs3_bnds = regs->cs[i].bnds;
+ ddr->cs3_config = regs->cs[i].config;
+ }
+ }
+
+ /* Someone decided to use different names from the documentation... */
+ ddr->timing_cfg_3 = regs->timing_cfg_3;
+ ddr->timing_cfg_0 = regs->timing_cfg_0;
+ ddr->timing_cfg_1 = regs->timing_cfg_1;
+ ddr->timing_cfg_2 = regs->timing_cfg_2;
+ ddr->sdram_cfg_2 = regs->ddr_sdram_cfg_2;
+ ddr->sdram_mode_1 = regs->ddr_sdram_mode;
+ ddr->sdram_mode_2 = regs->ddr_sdram_mode_2;
+ ddr->sdram_interval = regs->ddr_sdram_interval;
+ ddr->sdram_data_init = regs->ddr_data_init;
+ ddr->sdram_clk_cntl = regs->ddr_sdram_clk_cntl;
+ ddr->init_addr = regs->ddr_init_addr;
+ ddr->init_ext_addr = regs->ddr_init_ext_addr;
+
+ /* FIXME: ECC? Need to program err_disable, err_sbe, and err_int_en */
+ printf("before go\n");
+
+ /*
+ * 200 painful micro-seconds must elapse between
+ * the DDR clock setup and the DDR config enable.
+ */
+ udelay(200);
+ asm volatile("sync;isync");
+
+ ddr->sdram_cfg_1 = regs->ddr_sdram_cfg;
+
+ /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done */
+ while (ddr->sdram_cfg_2 & 0x10) {
+ udelay(10000); /* throttle polling rate */
+ }
+}
+
+unsigned int fsl_ddr_type_function(void)
+{
+ return SDRAM_TYPE_DDR2;
+}
+
+/*
+ * factors to consider for clock adjust:
+ * - number of chips on bus
+ * - position of slot
+ * - DDR1 vs. DDR2?
+ * - ???
+ *
+ * FIXME: need to figure out the function parameters necessary to compute
+ * FIXME: a clock adjust value
+ */
+unsigned int fsl_ddr_clk_adjust_function(void)
+{
+ return 7;
+}
+
+/*
+ * factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ *
+ * FIXME: figure out how to compute or tabulate good values for this
+ */
+unsigned int fsl_ddr_cpo_override_function(void)
+{
+ return 10;
+}
+
+/*
+ * factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+unsigned int fsl_ddr_write_data_delay_function(void)
+{
+ return 3;
+}
+
+/*
+ * factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+unsigned int fsl_ddr_half_strength_driver_enable_function(void)
+{
+ return 0;
+}
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index ff1b892..34f845e 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -33,6 +33,7 @@
#include <spd_sdram.h>
#include "../common/pixis.h"
+#include "../cpu/mpc8xxx/fsl_ddr_sdram.h"
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
@@ -122,7 +123,7 @@ initdram(int board_type)
long dram_size = 0;
#if defined(CONFIG_SPD_EEPROM)
- dram_size = spd_sdram();
+ dram_size = fsl_ddr_sdram();
#else
dram_size = fixed_sdram();
#endif
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index e9371a2..e8d80b1 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -8,7 +8,6 @@
/*
* MPC8610HPCD board configuration file
- *
*/
#ifndef __CONFIG_H
@@ -45,14 +44,6 @@
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_SPD_EEPROM /* Use SPD for DDR */
-#undef CONFIG_DDR_DLL /* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */
@@ -92,22 +83,46 @@
/*
* DDR Setup
*/
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM /* Use SPD for DDR */
+#define CONFIG_DDR_SPD
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM
#define MPC86xx_DDR_SDRAM_CLK_CNTL
-#if defined(CONFIG_SPD_EEPROM)
+
/*
- * Determine DDR configuration from I2C interface.
+ * Number of memory controllers on device
*/
-#define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */
-#else
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+
+/*
+ * Number of DIMM slots per memory controller
+ */
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+
/*
- * Manually set up DDR1 parameters
+ * Number of chip selects per memory controller
*/
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+
+/*
+ * I2C addresses of SPD EEPROMs
+ */
+#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
+
+/*
+ * These are used when DDR doesn't use SPD.
+ */
#define CFG_SDRAM_SIZE 256 /* DDR is 256MB */
#if 0 /* TODO */
@@ -130,7 +145,10 @@
#define CFG_DDR_ERR_INT_EN 0x00000000
#define CFG_DDR_ERR_DIS 0x00000000
#define CFG_DDR_SBE 0x000f0000
- /* Not used in fixed_sdram function */
+
+/*
+ * FIXME: Not used in fixed_sdram function
+ */
#define CFG_DDR_MODE 0x00000022
#define CFG_DDR_CS1_BNDS 0x00000000
#define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */
@@ -138,7 +156,7 @@
#define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */
#define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */
#endif
-#endif
+
#define CONFIG_ID_EEPROM
#define CFG_I2C_EEPROM_NXID
--
1.5.5.1
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