[U-Boot] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit

thaoth thaoth at cybersoft-vn.com
Thu Aug 21 11:54:22 CEST 2008


Hi Nobuhiro Iwamatsu,

> I think that cpu_init is not carried out.
> I think that u-boot stopped on lowlevel_init function.

thaoth wrote:
> 
> In lowlevel_init function, I put a LED debugging function which turn on
> LED on debug board. It works.
>  
> 	mov.l	LED_A, r1
> 	mov.l	LED_D, r0
> 	mov.b	r0, @r1
> 
> LED_A:		.long	0xA1600000		/* LED_BASE address */
> LED_D:		.long	0xaa			/* mh a1600000, 00  --> ALL LED ON */
> 
> But C function in sh_generic_init() cannot work. :(
> 

Here is lowlevel_init.S


> 	.global	lowlevel_init
> 
> 	.text
> 	.align	2
> 
> lowlevel_init:
> 	mov.l	WTCSR,r1		// WTCSR: 0xFFFFFF86 Watchdog Timer Control / Status
> Register)
> 	mov.l	WTCSR_D,r0		// WTCSR_D: 0xA506
> 	mov.w	r0, at r1
> 
> 	mov.l	WTCNT,r1		// WTCNT: 0xFFFFFF84 Watchdog Timer Counter
> 	mov.l	WTCNT_D,r0		// WTCNT_D: 0x5A00
> 	mov.w	r0, at r1
> 	
> !	mov.l	UCLKCR,r1		// UCLKCR: USBH/USBF Clock control register
> !	mov.l	UCLKCR_D,r0
> ! 	mov.w	r0, at r1
> 	
> 	mov.l	FRQCR, r1		// FRQCR_A: 0xFFFFFF80 Frequency control register
> Address
> 	mov.l	FRQCR_VAL, r0
> 	mov.w	r0, @r1
> 
> 	mov.l	BCR1, r1
> 	mov.l	BCR1_VAL, r0
> 	mov.w	r0, @r1			// base control register 1
> 
> 	mov.l	BCR2, r1
> 	mov.l	BCR2_VAL, r0
> 	mov.w	r0, @r1			// base control register 2
> 
> 	mov.l	WCR1, r1
> 	mov.l	WCR1_VAL, r0
> 	mov.w	r0, @r1			// wait state control register 1
> 
> 	mov.l	WCR2, r1
> 	mov.l	WCR2_VAL, r0
> 	mov.w	r0, @r1			// wait state control register 2
> 
> 	mov.l	MCR, r1
> 	mov.l	MCR_VAL, r0
> 	mov.w	r0, @r1			// memory control register
> 
> 	mov.l	PCR, r1
> 	mov.l	PCR_VAL, r0
> 	mov.w	r0, @r1			// PCMCIA control register
> 
> 	mov.l	RTCSR, r1
> 	mov.w	RTCSR_DUMMY, r0
> 	mov.w	r0, @r1			// reflash timer control / status register
> 
> 	mov.l	RTCNT, r1
> 	mov.w	RTCNT_VAL, r0
> 	mov.w	r0, @r1			// reflash timer counter
> 
> 	mov.l	RTCOR, r1
> 	mov.w	RTCOR_VAL, r0
> 	mov.w	r0, @r1			// reflash time constant counter
> 
> 	mov.l	RFCR, r1
> 	mov.w	RFCR_VAL, r0
> 	mov.w	r0, @r1			// reflash count register
> 
> 	/* SDRAM initalization */
> 	// 100us dummy wait
> 
> 	mov.l	SDMR3_ADDR, r1
> 	mov.w	SDMR3_VAL, r0
> 	mov.w	r0, @r1			// reflash count register
> 
> 	mov.l	RTCSR, r1
> 	mov.w	RTCSR_VAL, r0
> 	mov.w	r0, @r1			// reflash timer control / status register
> 
> 	// dummy reflash
> 	/***********************/
> 
> //	mov.l	_PINTER, r1		// init PINTER
> //	mov	#0, r0
> //	mov.w	r0, @r1
> 
> //	mov.l	_IPRA, r1		// init IPRA
> //	mov.w	IPRA_VAL, r0
> //	mov.w	r0, @r1
> 
> //	mov.l	_IPRD, r1		// init IPRD
> //	mov.w	IPRD_VAL, r0
> //	mov.w	r0, @r1
> 
> //	mov.l	_IPRG, r1		// init IPRG
> //	mov.w	IPRG_VAL, r0
> //	mov.w	r0, @r1
> 
> //	mov.l	_ICR1, r1		// init ICR1
> //	mov.w	ICR1_VAL, r0
> //	mov.w	r0, @r1
> 
> //	mov.l	_ICR2, r1		// init ICR2
> //	mov.w	ICR2_VAL, r0
> //	mov.w	r0, @r1
> 
> //	mov.l	_PINTER, r1		// init PINTER
> //	mov.w	PINTER_VAL, r0
> //	mov.w	r0, @r1
> 
> 	mov.l	PCCR, r1		// init PCCR
> 	mov.w	PCCR_VAL, r0
> 	mov.w	r0, @r1
> 
> 	mov.l	PDCR, r1		// init PDCR
> 	mov.w	PDCR_VAL, r0
> 	mov.w	r0, @r1
> 
> 	mov.l	PECR, r1		// init PECR
> 	mov.w	PECR_VAL, r0
> 	mov.w	r0, @r1
> 
> 	mov.l	PHCR, r1		// init PHCR
> 	mov.w	PHCR_VAL, r0
> 	mov.w	r0, @r1
> 
> 	mov.l	PJCR, r1		// init PJCR
> 	mov.w	PJCR_VAL, r0
> 	mov.w	r0, @r1
> 
> 	mov.l	PKCR, r1		// init PKCR
> 	mov.w	PKCR_VAL, r0
> 	mov.w	r0, @r1
> 
> 	mov.l	PLCR, r1		// init PLCR
> 	mov.w	PLCR_VAL, r0
> 	mov.w	r0, @r1
> 
> 	mov.l	PMCR, r1		// init PMCR
> 	mov.w	PMCR_VAL, r0
> 	mov.w	r0, @r1
> 
> 	mov.l	SCPCR, r1		// init SCPCR
> 	mov.w	SCPCR_VAL, r0
> 	mov.w	r0, @r1
> 
> !	mov.l	ICLK, r1		// init internal clock 96 Mhz
> !	mov.l	ICLK_VAL, r0
> !	mov.w	r0, @r1
> 
> !	mov.l	PCLK, r1		// init peripheral clock 24 Mhz
> !	mov.l	PCLK_VAL, r0
> !	mov.w	r0, @r1
> 
> 	mov.l	LED_A, r1
> 	mov.l	LED_D, r0
> 	mov.b	r0, @r1
> 	
> 	rts
> 	nop
> 
> 	.align 4
> 
> !ICLK:		.long	0x8c000274
> !PCLK:		.long	0x8c000276
> 
> WTCSR:	    .long	0xFFFFFF86	/* WTCSR: 0xFFFFFF86 Watchdog Timer Control /
> Status Register) */
> WTCNT:	    .long	0xFFFFFF84	/* WTCNT: 0xFFFFFF84 Watchdog Timer Counter */
> /*UCLKCR:	.long	0xA40A0008*/	/* USBH/USBF: Clock control register ???*/
> FRQCR:		.long	0xffffff80
> BCR1:		.long	0xffffff60      /* Bus Control Register 1 */
> BCR2:		.long	0xffffff62      /* Bus Control Register 2 */
> WCR1:		.long	0xffffff64      /* Wait State Control Register 1 */
> WCR2:		.long	0xffffff66      /* Wait State Control Register 2 */
> MCR:		.long	0xffffff68      /* Individual Memory Control Register */
> PCR:		.long	0xffffff6c      /* PCMCIA control register */
> RTCSR:		.long	0xffffff6e      /* Refresh timer control/status register */
> RTCNT:		.long	0xffffff70      /* Refresh timer counter */
> RTCOR:		.long	0xffffff72      /* Refresh time contant register */
> RFCR:		.long	0xffffff74      /* Refresh count register */
> SDMR3_ADDR:	.long	0xFFFFE800 + 0x80   /* Synchorounos DRAM Mode register
> ??? */
> 
> /* SH Internal Use - Area 1 */
> PCCR:		.long	0xa4000104
> PDCR:		.long	0xa4000106
> PECR:		.long	0xa4000108
> PFCR:		.long	0xa400010a
> PGCR:		.long	0xa400010c
> PHCR:		.long	0xa400010e
> PJCR:		.long	0xa4000110
> PKCR:		.long	0xa4000112
> PLCR:		.long	0xa4000114
> PMCR:		.long	0xa4000118
> SCPCR:		.long	0x04000116
> 
> /* Initialize data */
> ICLK_VAL:	.long	0x0060		// 96 Mhz
> PCLK_VAL:	.long	0x0018		// 24 Mhz
> 
> WTCNT_D:	.long	0x5A00		/* WTCNT_D: 0x5A00 set the upper byte to 5A and
> transfer data into lower byte */
> WTCSR_D:	.long	0xA506		/* WTCSR_D: 0xA506 set the upper byte to A5 and
> transfer data into lower byte */
> /*UCLKCR_D:	.long	0xA5C0*/
> 
> FRQCR_VAL:	.long	0x0112		// PLL*2, IFC*1, PFC/4
> BCR1_VAL:	.long	0x0008      /* Bus Control Register 1 */
> BCR2_VAL:	.long	0x2ae0      /* Bus Control Register 2 */
> #if USE_R0P7727TH003TRK == 1
> WCR1_VAL:	.long	0xaaa2      /* Wait State Control Register 1 */
> #else // previous type T-Engine
> WCR1_VAL:	.long	0xaa22
> #endif
> WCR2_VAL:	.long	0xb6dd      /* Wait State Control Register 2 */
> 
> #if USE_R0P7727TH003TRK == 1
> MCR_VAL:	.long	0x966c      /* Individual Memory Control Register */
> #else // previous type T-Engine
> MCR_VAL:	.long	0x012c
> #endif
> PCR_VAL:	.long	0x0000      /* PCMCIA control register */
> RTCSR_DUMMY:	.long	0xa500	// 
> RTCSR_VAL:	.long	0xa518		/* Refresh timer control/status register : CKIO
> 1/64 */
> RTCNT_VAL:	.long	0xa500      /* Refresh timer counter */
> 
> #if USE_R0P7727TH003TRK == 1
> RTCOR_VAL:	.long	0xa505		/* Refresh time contant register */ 
> #else // previous type T-Engine
> RTCOR_VAL:	.long	0xa50b		// 48MHz /64 14.667us
> #endif
> RFCR_VAL:	.long	0xa400      /* Refresh count register */
> SDMR3_VAL:	.long	0x00        /* Synchorounos DRAM Mode register ??? */
> 
> IPRA_VAL:	.long	0x8000
> IPRD_VAL:	.long	0xc000
> IPRG_VAL:	.long	0xc000
> ICR1_VAL:	.long	0x42aa
> ICR2_VAL:	.long	0x000c
> PINTER_VAL:	.long	0x000c
> PCCR_VAL:	.long	0x0000
> PDCR_VAL:	.long	0x0000
> PECR_VAL:	.long	0x0500
> PFCR_VAL:	.long	0x00AA
> PGCR_VAL:	.long	0xA200
> PHCR_VAL:	.long	0x0800
> PJCR_VAL:	.long	0x0540
> PKCR_VAL:	.long	0x0005
> PLCR_VAL:	.long	0xaaaa
> PMCR_VAL:	.long	0xaa00
> SCPCR_VAL:	.long	0x0000
> 
> SDCR_D1:	.long	0x00000011
> SDCR_D2:	.long	0x00000811
> 
> LED_A:		.long	0xA1600000		/* LED_BASE address */
> LED_D:		.long	0xaa			/* mh a1600000, 00  --> ALL LED ON */
> 

void sh_generic_init (void)
{
...
	outw(0x7e, LED_BASE);
}

Now sh_generic_init could be called with LEDs indicated true status. :-) But
I don't know what next issue? :-((

Best regards,
-- 
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