[U-Boot] [PATCH] Resubmit: Correct ARM Versatile Timer Initialization

[Gururaja Hebbar K R]

 - According to ARM Dual-Timer Module (SP804) TRM (ARM DDI0271),
   -- Timer Value Register @ TIMER Base + 4 is Read-only.
   -- Prescale Value (Bits 3-2 of TIMER Control register)
  	can only be one of 00,01,10. 11 is undefined.
   -- CFG_HZ for Versatile board is set to
  	#define CFG_HZ                  (1000000 / 256)
      So Prescale bits is set to indicate
  	- 8 Stages of Prescale, Clock divided by 256
 - The Timer Control Register has one Undefined/Shouldn't Use Bit
   So we should do read/modify/write Operation


Signed-off-by: Gururaja Hebbar <gururajakr at sanyo.co.in>
---
 cpu/arm926ejs/versatile/timer.c |   37 +++++++++++++++++++++++++++++++++----
 1 files changed, 33 insertions(+), 4 deletions(-)

diff --git a/cpu/arm926ejs/versatile/timer.c b/cpu/arm926ejs/versatile/timer.c
index 32872d2..17ba387 100755
--- a/cpu/arm926ejs/versatile/timer.c
+++ b/cpu/arm926ejs/versatile/timer.c
@@ -46,12 +46,41 @@
 static ulong timestamp;
 static ulong lastdec;
 
-/* nothing really to do with interrupts, just starts up a counter. */
+#define TIMER_ENABLE	(1 << 7)
+#define TIMER_MODE_MSK	(1 << 6)
+#define TIMER_MODE_FR	(0 << 6)
+#define TIMER_MODE_PD	(1 << 6)
+
+#define TIMER_INT_EN	(1 << 5)
+#define TIMER_PRS_MSK	(3 << 2)
+#define TIMER_PRS_8S	(1 << 3)
+#define TIMER_SIZE_MSK	(1 << 2)
+#define TIMER_ONE_SHT	(1 << 0)
+
 int timer_init (void)
 {
-	*(volatile ulong *)(CFG_TIMERBASE + 0) = CFG_TIMER_RELOAD;	/* TimerLoad */
-	*(volatile ulong *)(CFG_TIMERBASE + 4) = CFG_TIMER_RELOAD;	/* TimerValue */
-	*(volatile ulong *)(CFG_TIMERBASE + 8) = 0x8C;
+	ulong	TmrCntrlVal;
+
+	/*1st disable the Timer*/
+	TmrCntrlVal = *(volatile ulong *)(CFG_TIMERBASE + 8);
+	TmrCntrlVal &= ~TIMER_ENABLE;
+	*(volatile ulong *)(CFG_TIMERBASE + 8) = TmrCntrlVal;
+
+	/* The Timer Control Register has one Undefined/Shouldn't Use Bit
+	 * So we should do read/modify/write Operation
+	*/
+
+	/* Timer Mode : Free Running
+	 * Interrupt : Disabled
+	 * Prescale : 8 Stage,  Clk/256
+	 * Tmr Siz : 16 Bit Counter
+	 * Tmr in Wrapping Mode
+	*/
+	TmrCntrlVal = *(volatile ulong *)(CFG_TIMERBASE + 8);
+	TmrCntrlVal &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT );
+	TmrCntrlVal |= (TIMER_ENABLE | TIMER_PRS_8S);
+
+	*(volatile ulong *)(CFG_TIMERBASE + 8) = TmrCntrlVal;
 
 	/* init the timestamp and lastdec value */
 	reset_timer_masked();
-- 
1.5.6.4