[U-Boot] [PATCH 08/24] FSL DDR: Convert MPC8548CDS to new DDR code.
Kumar Gala
galak at kernel.crashing.org
Wed Aug 27 08:10:41 CEST 2008
From: Jon Loeliger <jdl at freescale.com>
Signed-off-by: Jon Loeliger <jdl at freescale.com>
Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
---
board/freescale/mpc8548cds/Makefile | 1 +
board/freescale/mpc8548cds/ddr.c | 80 +++++++++++++++++++++++++++++++
board/freescale/mpc8548cds/mpc8548cds.c | 8 +++-
include/configs/MPC8548CDS.h | 37 ++++++++-------
4 files changed, 108 insertions(+), 18 deletions(-)
create mode 100644 board/freescale/mpc8548cds/ddr.c
diff --git a/board/freescale/mpc8548cds/Makefile b/board/freescale/mpc8548cds/Makefile
index 98f1530..c19a527 100644
--- a/board/freescale/mpc8548cds/Makefile
+++ b/board/freescale/mpc8548cds/Makefile
@@ -27,6 +27,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += $(BOARD).o
+COBJS-y += ddr.o
COBJS-y += law.o
COBJS-y += tlb.o
diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c
new file mode 100644
index 0000000..f07d746
--- /dev/null
+++ b/board/freescale/mpc8548cds/ddr.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+
+static void
+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+ i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+ return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+
+ if (ctrl_num) {
+ printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+ return;
+ }
+
+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+ get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
+ }
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for clock adjust:
+ * - number of chips on bus
+ * - position of slot
+ * - DDR1 vs. DDR2?
+ * - ???
+ *
+ * This needs to be determined on a board-by-board basis.
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ popts->clk_adjust = 7;
+
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 10;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 3;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 0b037cc..84d3850 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -25,8 +25,10 @@
#include <common.h>
#include <pci.h>
#include <asm/processor.h>
+#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/immap_fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
#include <spd_sdram.h>
#include <miiphy.h>
#include <libfdt.h>
@@ -111,7 +113,10 @@ initdram(int board_type)
udelay(200);
}
#endif
- dram_size = spd_sdram();
+
+ dram_size = fsl_ddr_sdram();
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
@@ -119,6 +124,7 @@ initdram(int board_type)
*/
ddr_enable_ecc(dram_size);
#endif
+
/*
* SDRAM Initialization
*/
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 33c5c93..ec0b4ff 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -46,15 +46,7 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_DLL /* possible DLL fix needed */
-#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
-
-#define CONFIG_DDR_ECC /* only for ECC DDR module */
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
-
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_VIA
@@ -67,8 +59,6 @@
*/
#define CONFIG_ASSUME_AMD_FLASH
-#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
-
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif
@@ -103,17 +93,27 @@ extern unsigned long get_clock_freq(void);
#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
-/*
- * DDR Setup
- */
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_DLL /* possible DLL fix needed */
+
+#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
-#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-/*
- * Make sure required options are set
- */
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
+
+/* Make sure required options are set */
#ifndef CONFIG_SPD_EEPROM
#error ("CONFIG_SPD_EEPROM is required")
#endif
@@ -342,6 +342,9 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+#define CFG_64BIT_VSPRINTF 1
+#define CFG_64BIT_STRTOUL 1
+
/*
* I2C
*/
--
1.5.5.1
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