[U-Boot] [PATCH 12/24] FSL DDR: Convert atum8548 to new DDR code.
Kumar Gala
galak at kernel.crashing.org
Wed Aug 27 08:10:45 CEST 2008
Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
---
board/atum8548/Makefile | 9 +++--
board/atum8548/atum8548.c | 8 +++-
board/atum8548/ddr.c | 80 ++++++++++++++++++++++++++++++++++++++++++++
include/configs/ATUM8548.h | 64 +++++++++++++++++------------------
4 files changed, 123 insertions(+), 38 deletions(-)
create mode 100644 board/atum8548/ddr.c
diff --git a/board/atum8548/Makefile b/board/atum8548/Makefile
index d2e689f..b991308 100644
--- a/board/atum8548/Makefile
+++ b/board/atum8548/Makefile
@@ -29,10 +29,13 @@ endif
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o law.o tlb.o
+COBJS-y += $(BOARD).o
+COBJS-y += law.o
+COBJS-y += tlb.o
+COBJS-$(CONFIG_FSL_DDR2) += ddr.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c
index 34f4599..337cf31 100644
--- a/board/atum8548/atum8548.c
+++ b/board/atum8548/atum8548.c
@@ -29,7 +29,9 @@
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/immap_fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
#include <asm/io.h>
+#include <asm/mmu.h>
#include <spd_sdram.h>
#include <miiphy.h>
#include <libfdt.h>
@@ -106,8 +108,10 @@ initdram(int board_type)
puts("Initializing\n");
#if defined(CONFIG_SPD_EEPROM)
- puts("spd_sdram\n");
- dram_size = spd_sdram ();
+ puts("fsl_ddr_sdram\n");
+ dram_size = fsl_ddr_sdram();
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
#else
puts("fixed_sdram\n");
dram_size = fixed_sdram ();
diff --git a/board/atum8548/ddr.c b/board/atum8548/ddr.c
new file mode 100644
index 0000000..f07d746
--- /dev/null
+++ b/board/atum8548/ddr.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+
+static void
+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+ i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+ return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+
+ if (ctrl_num) {
+ printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+ return;
+ }
+
+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+ get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
+ }
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for clock adjust:
+ * - number of chips on bus
+ * - position of slot
+ * - DDR1 vs. DDR2?
+ * - ???
+ *
+ * This needs to be determined on a board-by-board basis.
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ popts->clk_adjust = 7;
+
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 10;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 3;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h
index 6aa881c..5bc28f1 100644
--- a/include/configs/ATUM8548.h
+++ b/include/configs/ATUM8548.h
@@ -55,18 +55,11 @@
#define CONFIG_TSEC_ENET 1 /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for DDR setup*/
-#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
-#define CONFIG_DDR_ECC /* only for ECC DDR module */
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
-
#define CONFIG_SYS_CLK_FREQ 33000000
/*
@@ -104,33 +97,38 @@
#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
-/*
- * DDR Setup
- */
-#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
-#if defined(CONFIG_SPD_EEPROM)
- /*
- * Determine DDR configuration from I2C interface.
- */
- #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#else
- /*
- * Manually set up DDR parameters
- */
- #define CFG_SDRAM_SIZE 1024 /* DDR is 1024MB */
- #define CFG_DDR_CS0_BNDS 0x0000000f /* 0-1024 */
- #define CFG_DDR_CS0_CONFIG 0x80000102
- #define CFG_DDR_TIMING_0 0x00260802
- #define CFG_DDR_TIMING_1 0x38355322
- #define CFG_DDR_TIMING_2 0x039048c7
- #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
- #define CFG_DDR_MODE 0x00000432
- #define CFG_DDR_INTERVAL 0x05150100
- #define DDR_SDRAM_CFG 0x43000000
-#endif
+#define CFG_DDR_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
+
+/* Manually set up DDR parameters */
+#define CFG_SDRAM_SIZE 1024 /* DDR is 1024MB */
+#define CFG_DDR_CS0_BNDS 0x0000000f /* 0-1024 */
+#define CFG_DDR_CS0_CONFIG 0x80000102
+#define CFG_DDR_TIMING_0 0x00260802
+#define CFG_DDR_TIMING_1 0x38355322
+#define CFG_DDR_TIMING_2 0x039048c7
+#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
+#define CFG_DDR_MODE 0x00000432
+#define CFG_DDR_INTERVAL 0x05150100
+#define DDR_SDRAM_CFG 0x43000000
#undef CONFIG_CLOCKS_IN_MHZ
--
1.5.5.1
More information about the U-Boot
mailing list