[U-Boot-Users] [PATCH 1/3] ppc4xx: PPC405GPr add missing EIRR register

[Niklaus Giger]

Stefan Roese wrote:

> Hi Niklaus,
> 
> On Monday 04 February 2008, Niklaus Giger wrote:
>> Signed-off-by: Niklaus Giger <niklaus.giger at netstal.com>
> 
> Thanks for splitting this out. But still I have a question. See below.
> 
>> ---
>>  include/ppc405.h |    4 ++++
>>  1 files changed, 4 insertions(+), 0 deletions(-)
>>
>> diff --git a/include/ppc405.h b/include/ppc405.h
>> index b5ad38f..fbfb681 100644
>> --- a/include/ppc405.h
>> +++ b/include/ppc405.h
>> @@ -784,6 +784,10 @@
>>  #define reset   (CNTRL_DCR_BASE+0x3)  /* reset register                          */
>>  #define strap   (CNTRL_DCR_BASE+0x4)  /* strap register                          */
>>
>> +#ifdef CONFIG_405GPr
>> +#define eirr    (CNTRL_DCR_BASE+0x6)  /* external interrupt routing
>> register */ +#endif
>> +
> 
> Why is 405GPr needed here? Is this register not available in 405GP?
I found the following comments in the Migration guide for the PPC405GP ->
PPC405GPr (PPC405GP_AN2023_405GPrMigration__v1_01.pdf).
> The 405GPr provides the ability to add six external interrupts to the 
> seven already available on the 405GP. This is accomplished by logic that
> allows routing any of the 24 GPIOs to six  previously unused Universal 
> Interrupt Controller (UIC) inputs. For those GPIOs that are shared with  
> other functions, the corresponding I/O must first be configured via
> CPC0_CR0 to be a GPIO. Table 14 shows how the new GPIO to UIC External
> Interrupt Routing Register (CPC0_EIRR) logically routes GPIO inputs used
> as interrupts to the UIC.    
Therefore I concluded that it is very PPC405GPr specific. But I did not
check all other PPC405 variants.

Best regards

Niklaus