[U-Boot-Users] 440EPX is not booting from 1Gb/128MB NAND flash

[Nikhil Gautam]

Hi Stefan,

After some debugging using BDI, I found out that there are more then
one problem here.

IPL loads the SPL correctly. And I can see that nand_boot( ) is
called. The first problem I found was that the nand_is_bad_block( ) is
returning true after a while. I think its treating empty blocks as bad
blocks. I know there are no bad blocks because I booted using the NOR
image and then checked the NAND flash.

Secondly, the SPL is copying the u-boot image to ram incorrectly. By
this I mean, when I do the memory dump of RAM where U-boot image
should be loaded, only the first NAND page (2K) is copied correctly.
After that it's random or empty.

The third problem is that in the board config file
#define CFG_NAND_U_BOOT_OFFS	(16 << 10)
is incorrect for current U-boot. If you look at nand_boot.c
	/*
	 * offs has to be aligned to a block address!
	 */
	block = CFG_NAND_U_BOOT_OFFS / CFG_NAND_BLOCK_SIZE;

This is because this file copies sectors completely. For 2k page size
and 64 pages per block, The SPL is again copying the complete NAND
flash from address "0" to RAM.

Changing this define to
#define CFG_NAND_U_BOOT_OFFS	(128 << 10)
will not help because when u-boot is compiles, it pads the image
enough so that the U-Boot ram image is always located at 16K. Do you
know how can I change it to that my new U-boot ram image starts from
128K offset.

Thanks

Nikhil Gautam

On Feb 7, 2008 8:50 PM, Stefan Roese <sr at denx.de> wrote:
> On Friday 08 February 2008, Nikhil Gautam wrote:
> > I figured couple of more things that needed change
> >
> > In ndfc.c
> > #ifdef CFG_NAND_4_ADDR_CYCLE
> >        /* Set NandFlash Core Configuration Register */
> >        /* 2 col x 2 rows */
> >        out32(base + NDFC_CCR, 0x00002000 | (cs << 24));
> > #else
> >        /* Set NandFlash Core Configuration Register */
> >        /* 1 col x 2 rows */
> >        out32(base + NDFC_CCR, 0x00000000 | (cs << 24));
> > #endif /* CFG_NAND_4_ADDR_CYCLE */
>
> I don't think this change is needed. This only affects "auto-read" mode, so
> the first stage NAND boot loader (IPL), that loads the 4k SPL which we are
> talking about right now into memory. But you have to configure the
> corresponding bits in the bootstrap EEPROM correctly of course.
>
> > Also for 1Gb NAND flash, the address fetch is different then 256Mb,
> > here is what I changed
> >
> > #ifdef CFG_NAND_4_ADDR_CYCLE
> >        /* Column address */
> >        this->write_byte(mtd, 0);
> > /* A[7:0] */
> >        this->write_byte(mtd, (uchar)(page_addr & 0x0f));
> > /* A[11:8] */
> >        this->write_byte(mtd, (uchar)((page_addr >> 4) & 0xff));
> > /* A[19:12] */
> >        /* One more address cycle for devices > 32MiB */
> >        this->write_byte(mtd, (uchar)((page_addr >> 12) & 0xff));
> > /* A[27:20] */
> > #else
> >        /* Column address */
> >        this->write_byte(mtd, 0);
> > /* A[7:0] */
> >        this->write_byte(mtd, (uchar)(page_addr & 0xff));
> > /* A[16:9] */
> >        this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff));
> > /* A[24:17] */
> > #endif
>
> This doesn't match the 4 address cycle mode used for bigger 512k page devices.
> I think we may need another config define for 2k page devices.
>
> > Even with these two changes, the board is not booting??
>
> And where does it hang? Did you have a chance to see where execution stops? Is
> nand_boot() called at all?
>
> I suggest to debug things extensively with an BDI2000.
>
>
> Best regards,
> Stefan
>
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