[U-Boot-Users] [PATCH v2] PPC440EPx: Reconfigure PLL for 667MHz processor

[Stefan Roese]

Mike,

On Wednesday 20 February 2008, Mike Nuss wrote:
> > don't you think this is a little bit to shortsighted?
> > There are many other parameters beyond the CPU clock that could be
> > modified in such a way. We have some code in the PMC440 board
> > code that sets up the PCI sync clock dynamically dependant on
> > a GPIO (M66EN pci pin). So I would vote for a more generic
> > configuration than
> > by a CPU frequency parameter. Just think about this: should
> > 667 MHz on an EPx
> > always mean 166 MHz PLB clock? 667MHZ with 133MHz PLB might also be
> > a typical configuration (e.g. when you need 66MHz EBC clock ....).
> >
> > So what about a function that takes the complete strapping values
> > as parameters (I think 4 longs) instead of nothing but the
> > CPU frequency.
>
> I agree that this could be much more configurable. Apparently no one has
> needed those options yet, as there currenntly isn't any code to reconfigure
> the clocks at all. I would guess most people are using an EEPROM to set
> things up.

Right. All boards I have seem so far, are equipped with such an EEPROM. And I 
would always recommend to add it to a 4xx design.

> As for shortsightedness, keep in mind that I'm not a full time U-Boot
> developer. I solved a problem to get our board working and I'm happy to
> share the solution I came up with, but I just don't have the resources to
> solve a problem that someone else might have later. IMO, with the basics in
> this patch, it should be easy enough for anyone to modify it for additional
> configurations if they are needed.

Yes, I understand your situation. Thanks for changing the patch as I 
suggested. I'm inclined to accept your patch (if nobody objects) as is for 
the next merge window. If somebody needs an extended version of this PLL 
reconfiguration, he or she can easily adapt your code.

Thanks.

Best regards,
Stefan

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