[U-Boot-Users] [PATCH] QE UEC: Add CMD_MII support, extend number of supported UECs to 4
David Saada
David.Saada at ecitele.com
Thu Jan 3 18:25:34 CET 2008
Description: QE UEC: Add CMD_MII support, extend number of supported
UECs to 4
Signed-off-by: David Saada <david.saada at ecitele.com>
> diff -purN net/eth.c.orig net/eth.c
--- net/eth.c.orig Wed Jan 2 13:39:04 2008
+++ net/eth.c Thu Jan 3 18:44:45 2008
@@ -202,7 +202,12 @@ int eth_initialize(bd_t *bis)
#if defined(CONFIG_UEC_ETH2)
uec_initialize(1);
#endif
-
+#if defined(CONFIG_UEC_ETH3)
+ uec_initialize(2);
+#endif
+#if defined(CONFIG_UEC_ETH4)
+ uec_initialize(3);
+#endif
#if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
fec_initialize(bis);
#endif
> diff -purN drivers/qe/uec.c.orig drivers/qe/uec.c
--- drivers/qe/uec.c.orig Wed Jan 2 13:39:04 2008
+++ drivers/qe/uec.c Thu Jan 3 17:23:17 2008
@@ -29,6 +29,7 @@
#include "uccf.h"
#include "uec.h"
#include "uec_phy.h"
+#include "miiphy.h"
#if defined(CONFIG_QE)
@@ -40,8 +41,13 @@ static uec_info_t eth1_uec_info = {
.tx_clock = CFG_UEC1_TX_CLK,
.eth_type = CFG_UEC1_ETH_TYPE,
},
+#ifdef CFG_UEC1_NUM_TX_RX_THR
+ .num_threads_tx = CFG_UEC1_NUM_TX_RX_THR,
+ .num_threads_rx = CFG_UEC1_NUM_TX_RX_THR,
+#else
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
+#endif
.riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
@@ -58,8 +64,13 @@ static uec_info_t eth2_uec_info = {
.tx_clock = CFG_UEC2_TX_CLK,
.eth_type = CFG_UEC2_ETH_TYPE,
},
+#ifdef CFG_UEC2_NUM_TX_RX_THR
+ .num_threads_tx = CFG_UEC2_NUM_TX_RX_THR,
+ .num_threads_rx = CFG_UEC2_NUM_TX_RX_THR,
+#else
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
+#endif
.riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
@@ -68,6 +79,63 @@ static uec_info_t eth2_uec_info = {
.enet_interface = CFG_UEC2_INTERFACE_MODE,
};
#endif
+#ifdef CONFIG_UEC_ETH3
+static uec_info_t eth3_uec_info = {
+ .uf_info = {
+ .ucc_num = CFG_UEC3_UCC_NUM,
+ .rx_clock = CFG_UEC3_RX_CLK,
+ .tx_clock = CFG_UEC3_TX_CLK,
+ .eth_type = CFG_UEC3_ETH_TYPE,
+ },
+#ifdef CFG_UEC3_NUM_TX_RX_THR
+ .num_threads_tx = CFG_UEC3_NUM_TX_RX_THR,
+ .num_threads_rx = CFG_UEC3_NUM_TX_RX_THR,
+#else
+ .num_threads_tx = UEC_NUM_OF_THREADS_4,
+ .num_threads_rx = UEC_NUM_OF_THREADS_4,
+#endif
+ .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .tx_bd_ring_len = 16,
+ .rx_bd_ring_len = 16,
+ .phy_address = CFG_UEC3_PHY_ADDR,
+ .enet_interface = CFG_UEC3_INTERFACE_MODE,
+};
+#endif
+#ifdef CONFIG_UEC_ETH4
+static uec_info_t eth4_uec_info = {
+ .uf_info = {
+ .ucc_num = CFG_UEC4_UCC_NUM,
+ .rx_clock = CFG_UEC4_RX_CLK,
+ .tx_clock = CFG_UEC4_TX_CLK,
+ .eth_type = CFG_UEC4_ETH_TYPE,
+ },
+#ifdef CFG_UEC4_NUM_TX_RX_THR
+ .num_threads_tx = CFG_UEC4_NUM_TX_RX_THR,
+ .num_threads_rx = CFG_UEC4_NUM_TX_RX_THR,
+#else
+ .num_threads_tx = UEC_NUM_OF_THREADS_4,
+ .num_threads_rx = UEC_NUM_OF_THREADS_4,
+#endif
+ .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .tx_bd_ring_len = 16,
+ .rx_bd_ring_len = 16,
+ .phy_address = CFG_UEC4_PHY_ADDR,
+ .enet_interface = CFG_UEC4_INTERFACE_MODE,
+};
+#endif
+
+#define MAXCONTROLLERS (4)
+
+static uec_private_t *privlist[MAXCONTROLLERS];
+
+static int uec_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value);
+static int uec_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value);
+u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
+void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
{
@@ -1238,11 +1306,21 @@ int uec_initialize(int index)
#ifdef CONFIG_UEC_ETH2
uec_info = ð2_uec_info;
#endif
+ } else if (index == 2) {
+#ifdef CONFIG_UEC_ETH3
+ uec_info = ð3_uec_info;
+#endif
+ } else if (index == 3) {
+#ifdef CONFIG_UEC_ETH4
+ uec_info = ð4_uec_info;
+#endif
} else {
printf("%s: index is illegal.\n", __FUNCTION__);
return -EINVAL;
}
+ privlist[index] = uec;
+
uec->uec_info = uec_info;
sprintf(dev->name, "FSL UEC%d", index);
@@ -1273,6 +1351,73 @@ int uec_initialize(int index)
phy_change(dev);
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
+ && !defined(BITBANGMII)
+ miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write);
+#endif
+
return 1;
}
+
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
+ && !defined(BITBANGMII)
+
+uec_private_t *uec_get_priv_for_phy(unsigned char phyaddr)
+{
+ int i;
+
+ for (i = 0; i < MAXCONTROLLERS; i++) {
+ if (privlist[i]->uec_info->phy_address == phyaddr)
+ return privlist[i];
+ }
+
+ return NULL;
+}
+
+/*
+ * Read a MII PHY register.
+ *
+ * Returns:
+ * 0 on success
+ */
+static int uec_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value)
+{
+ unsigned short ret;
+ uec_private_t *priv = uec_get_priv_for_phy(addr);
+
+ if (NULL == priv) {
+ printf("Can't read PHY at address %d\n", addr);
+ return -1;
+ }
+
+ ret = phy_read(priv->mii_info, reg);
+ *value = ret;
+
+ return 0;
+}
+
+/*
+ * Write a MII PHY register.
+ *
+ * Returns:
+ * 0 on success
+ */
+static int uec_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
+{
+ uec_private_t *priv = uec_get_priv_for_phy(addr);
+
+ if (NULL == priv) {
+ printf("Can't write PHY at address %d\n", addr);
+ return -1;
+ }
+
+ phy_write(priv->mii_info, reg, value);
+
+ return 0;
+}
+
+#endif
+
#endif /* CONFIG_QE */
More information about the U-Boot
mailing list