[U-Boot-Users] [PATCH] 86xx: Support 2GB DIMMs

[Jon Loeliger]

From: Becky Bruce <bgill at freescale.com>

Configure the number of bits used to address the banks inside the SDRAM
device.  The default register value of 0 means 2 bits to address 4 banks.
Higher capacity devices like a 2GB DIMM require 3 bits to address 8 banks.

Signed-off-by: Becky Bruce <bgill at freescale.com>
---
 cpu/mpc86xx/spd_sdram.c |   11 ++++++++++-
 1 files changed, 10 insertions(+), 1 deletions(-)

diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c
index 265e033..54e40f1 100644
--- a/cpu/mpc86xx/spd_sdram.c
+++ b/cpu/mpc86xx/spd_sdram.c
@@ -196,7 +196,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
 	spd_eeprom_t spd;
 	unsigned int n_ranks;
 	unsigned int rank_density;
-	unsigned int odt_rd_cfg, odt_wr_cfg;
+	unsigned int odt_rd_cfg, odt_wr_cfg, ba_bits;
 	unsigned int odt_cfg, mode_odt_enable;
 	unsigned int refresh_clk;
 #ifdef MPC86xx_DDR_SDRAM_CLK_CNTL
@@ -321,6 +321,10 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
 		odt_wr_cfg = 1;		/* Assert ODT on writes to CS0 */
 	}
 
+	ba_bits = 0;
+	if (spd.nbanks == 0x8)
+		ba_bits = 1;
+
 #ifdef CONFIG_DDR_INTERLEAVE
 
 	if (dimm_num != 1) {
@@ -357,6 +361,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
 #endif
 				    | (odt_rd_cfg << 20)
 				    | (odt_wr_cfg << 16)
+				    | (ba_bits << 14)
 				    | (spd.nrow_addr - 12) << 8
 				    | (spd.ncol_addr - 8) );
 
@@ -386,6 +391,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
 		ddr->cs0_config = ( 1 << 31
 				    | (odt_rd_cfg << 20)
 				    | (odt_wr_cfg << 16)
+				    | (ba_bits << 14)
 				    | (spd.nrow_addr - 12) << 8
 				    | (spd.ncol_addr - 8) );
 
@@ -403,6 +409,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
 			ddr->cs1_config = ( 1<<31
 					    | (odt_rd_cfg << 20)
 					    | (odt_wr_cfg << 16)
+					    | (ba_bits << 14)
 					    | (spd.nrow_addr - 12) << 8
 					    | (spd.ncol_addr - 8) );
 			debug("DDR: cs1_bnds   = 0x%08x\n", ddr->cs1_bnds);
@@ -422,6 +429,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
 		ddr->cs2_config = ( 1 << 31
 				    | (odt_rd_cfg << 20)
 				    | (odt_wr_cfg << 16)
+				    | (ba_bits << 14)
 				    | (spd.nrow_addr - 12) << 8
 				    | (spd.ncol_addr - 8) );
 
@@ -439,6 +447,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
 			ddr->cs3_config = ( 1<<31
 					    | (odt_rd_cfg << 20)
 					    | (odt_wr_cfg << 16)
+					    | (ba_bits << 14)
 					    | (spd.nrow_addr - 12) << 8
 					    | (spd.ncol_addr - 8) );
 			debug("DDR: cs3_bnds   = 0x%08x\n", ddr->cs3_bnds);
-- 
1.5.2.1.126.g6abd0