[U-Boot-Users] [PATCH] ppc4xx: Refactor ECC POST for AMCC Denali core

[Stefan Roese]

Hi Larry,

On Monday 14 January 2008, Larry Johnson wrote:
> I'm not convinced about in_be32() et al. yet.  Section 2.10.3 of the AMCC
> PPC440 User's manual says that an "msync" (sync) is required between the
> memory access and the control-register access.  ("mbar" (eieio) is not
> sufficient because the control-register access is not treated as I/O.)
>
> If I'm reading these correctly, in_be32() does a "sync", load, "twi"
> (which I don't understand), and "isync".  out_be32() does a "sync" and a
> store.  Thus, neither force completion of the I/O before exiting.
>
> Am I right then that I should include a specific sync before accessing
> the SDRAM control registers?

From your explanation above, it could make sense to add an additional sync 
between the memory access and the control register access. This would depend 
on the control register type and how it is accessed in the code. If it is a 
memory mapped register and accessed via the in_be32() functions, the 
additional sync is not needed. But if it is a SPR/DCR type of register, the 
sync makes sense to me.

Best regards,
Stefan

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