[U-Boot-Users] [RFC/PATCH] 85xx: Initial multicore boot support
Kumar Gala
galak at kernel.crashing.org
Tue Jan 22 10:31:18 CET 2008
On Jan 22, 2008, at 2:59 AM, Wolfgang Denk wrote:
> In message <Pine.LNX.
> 4.64.0801220214120.31981 at blarg.am.freescale.net> you wrote:
>> I was hoping to get some feed back on this patch that will add
>> support for
>> booting the multiprocessor 85xx chips. The boot mechanism is based
>> on the
>> forth coming ePAPR spec (based on how device tree, linux
>> booting-without-of spec).
>>
>> The biggest feedback I'm hoping for is related to the command set
>> and its
>> name:
>>
>> "cpu - CPU boot table manipulation and release\n",
>> "<num> reset - Reset cpu <num>\n"
>> "cpu <num> status - Status of cpu <num>\n"
>> "cpu <num> release <addr> - Release cpu <num> and start at <addr>\n"
>
> Above make ssense to me.
>
>> "cpu <num> pir <val> - Set cpu <num> PIR\n"
>> "cpu <num> r3 <val> - Set cpu <num> r3\n"
>> "cpu <num> r4 <val> - Set cpu <num> r4\n"
>> "cpu <num> r7 <val> - Set cpu <num> r7\n"
>
> But these are highly 85xx or at least PPC specific, it seems. If we
> design such a system, it should be able to deal with all kinds of MP
> systems, not only 85xx.
they are PPC specific, but they go to the boot interface and what the
"calling interface" looks like when release a processor out of spin.
I should have explained further how this works on 85xx/ppc. We end up
having a table. Each processor has an entry in the table with the
following fields:
* boot addr
* pir (processor id)
* r3
* r4
* r7
when a value other than '1' is written to the 'boot addr' field that
processor will come out of spin and load up r3, r4, r5, r6, r7 based
on the ePAPR calling convention (which pretty much says r3, r4, r7 are
passed in via FW, r5 is 0, and r6 is a magic #)
So I'm not sure if other architectures would adopt something similar
or not. In practice there isn't too much specific about the commands
to 85xx, but they are PPC specific.
I'm not sure how/what we should do about other arch's.
- k
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