[U-Boot-Users] [PATCH] 86xx: Add the concept of CFG_CCSRBAR_PHYS

[Kumar Gala]

When we go to 36-bit physical addresses we need to keep the concept of
the physical CCSRBAR address seperate from the virtual one.

For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR

Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
---
 cpu/mpc86xx/start.S           |    8 ++++----
 include/configs/MPC8610HPCD.h |    5 +++--
 include/configs/MPC8641HPCN.h |    5 +++--
 include/configs/sbc8641d.h    |    5 +++--
 4 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index f163521..40f0bdb 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -278,7 +278,7 @@ in_flash:
 	bl      clear_tlbs
 	sync

-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR_PHYS)
 	/* setup ccsrbar */
 	bl      setup_ccsrbar
 #endif
@@ -1027,15 +1027,15 @@ enable_ext_addr:
 	isync
 	blr

-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR_PHYS)
 .globl setup_ccsrbar
 setup_ccsrbar:
 	/* Special sequence needed to update CCSRBAR itself */
 	lis	r4, CFG_CCSRBAR_DEFAULT at h
 	ori	r4, r4, CFG_CCSRBAR_DEFAULT at l

-	lis	r5, CFG_CCSRBAR at h
-	ori	r5, r5, CFG_CCSRBAR at l
+	lis	r5, CFG_CCSRBAR_PHYS at h
+	ori	r5, r5, CFG_CCSRBAR_PHYS at l
 	srwi	r6,r5,12
 	stw	r6, 0(r4)
 	isync
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 3920147..a88a066 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -82,6 +82,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */

 #define CFG_PCI1_ADDR		(CFG_CCSRBAR+0x8000)
@@ -402,10 +403,10 @@
  * BAT4		4M	Cache-inhibited, guarded
  * 0xe000_0000	4M	CCSR
  */
-#define CFG_DBAT4L	(CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
+#define CFG_DBAT4L	(CFG_CCSRBAR_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 			| BATL_GUARDEDSTORAGE)
 #define CFG_DBAT4U	(CFG_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CFG_IBAT4L	(CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT4L	(CFG_CCSRBAR_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT4U	CFG_DBAT4U

 /*
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index a8d0077..73d0695 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -96,6 +96,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xf8000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */

 #define CFG_PCI1_ADDR		(CFG_CCSRBAR+0x8000)
@@ -461,10 +462,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * BAT3         4M     Cache-inhibited, guarded
  * 0xf800_0000  4M     CCSR
  */
-#define CFG_DBAT3L      ( CFG_CCSRBAR | BATL_PP_RW \
+#define CFG_DBAT3L      ( CFG_CCSRBAR_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CFG_DBAT3U      (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
-#define CFG_IBAT3L      (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT3L      (CFG_CCSRBAR_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT3U      CFG_DBAT3U

 /*
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 1991a8c..94cd2a8 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -96,6 +96,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xf8000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */

 #define CFG_PCI1_ADDR		(CFG_CCSRBAR+0x8000)
@@ -424,10 +425,10 @@
  * BAT3         4M     Cache-inhibited, guarded
  * 0xf800_0000  4M     CCSR
  */
-#define CFG_DBAT3L	( CFG_CCSRBAR | BATL_PP_RW \
+#define CFG_DBAT3L	( CFG_CCSRBAR_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CFG_DBAT3U	(CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
-#define CFG_IBAT3L	(CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT3L	(CFG_CCSRBAR_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT3U	CFG_DBAT3U

 /*
-- 
1.5.3.8