[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor
Jean-Christophe PLAGNIOL-VILLARD
plagnioj at jcrosoft.com
Tue Jul 8 12:32:29 CEST 2008
On 11:33 Tue 08 Jul , Jens Gehrlein wrote:
> Signed-off-by: Jens Gehrlein <sew_s at tqs.de>
> ---
>
> Fixed two bugs:
> a) added NFS mount option "rw" to default environment
> b) added prefix $(obj) in front of .depend in Makefile. Thank you Magnus for catching that.
>
>
> MAINTAINERS | 4
> MAKEALL | 1
> Makefile | 3
> board/tqc/tqma31/Makefile | 48 ++++
> board/tqc/tqma31/config.mk | 2
> board/tqc/tqma31/lowlevel_init.S | 375 +++++++++++++++++++++++++++++++++
> board/tqc/tqma31/tqma31.c | 95 ++++++++
> board/tqc/tqma31/u-boot.lds | 72 ++++++
> include/asm-arm/arch-mx31/mx31-regs.h | 42 ++++
> include/configs/TQMA31.h | 271 ++++++++++++++++++++++++
> 10 files changed, 913 insertions(+), 0 deletions(-)
> create mode 100644 board/tqc/tqma31/Makefile
> create mode 100644 board/tqc/tqma31/config.mk
> create mode 100644 board/tqc/tqma31/lowlevel_init.S
> create mode 100644 board/tqc/tqma31/tqma31.c
> create mode 100644 board/tqc/tqma31/u-boot.lds
> create mode 100644 include/configs/TQMA31.h
>
> +
> +COBJS := tqma31.o
why not use $(BOARD)?
COBJS := $(BOARD).o
> +SOBJS := lowlevel_init.o
> +
> +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS))
> +SOBJS := $(addprefix $(obj),$(SOBJS))
> +
> +#elif defined CONFIG_MX31_CPU_532_MHZ
> + /* Platform clocks */
> + REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) /* camera sensor interface */ \
> + | PDR0_PER_PODF(8-1) /* periph. if derived from USB clock */ \
> + | PDR0_HSP_PODF(4-1) /* IPU 133 MHz */ \
Please use tab instead of whitespace
> + | PDR0_NFC_PODF(7-1) /* NAND FC 19 MHz */ \
Please use tab instead of whitespace
> + | PDR0_IPG_PODF(2-1) /* peripherals 66.5 MHz */ \
Please use tab instead of whitespace
> + | PDR0_MAX_PODF(4-1) /* AHB 133 MHz */ \
Please use tab instead of whitespace
> + | PDR0_MCU_PODF(1-1) /* core 532 MHz */
> + /* MCU PLL */
> + REG CCM_MPCTL, PLL_PD(1-1) | PLL_MFD(52-1) | PLL_MFI(10) | PLL_MFN(12)
> +#else
> +#error Please define CPU core frequency (CONFIG_CPU_399_MHZ or CONFIG_CPU_532_MHZ)!
> +#endif /* CONFIG_CPU_xxx_MHZ */
> +
> + /* Serial PLL. Default: 1, 4, 12, 1 */
> + REG CCM_SPCTL, PLL_PD(2-1) | PLL_MFD(5-1) | PLL_MFI(12) | PLL_MFN(1)
> +.endm /* init_sdram */
> +
> +
> +/* setup SDRAM on CSD0 */
> +.macro init_sdram
> + /*
> + * Enhanced SDRAM Miscellaneous Register
> + * Latency Hiding Enable
> + * LPDDR delay line measure unit is enabled
> + * LPDDR Delay Line is not reset
> + * Enable Mobile DDR SDRAM operation
> + * Soft Reset is disabled
> + */
> + REG ESDMISC, 0x00000004
> +
> + /*
> + * Enhanced SDRAM Configuration Register 0
> + * tXP 4 clock delay before new COMMAND issued to LPDDR
> + * tWTR tLPDDR WRITE to READ Command Delay = 2 clock
> + * tRP SDRAM Row Precharge Delay = 3 clock
> + * tMRD–SDRAM Load Mode Register to ACTIVE Command = 3 clock
you have a nice char here '<96>' in vim
> + * tWR SDRAM WRITE to PRECHARGE Command = 3 clock
> + * tRAS SDRAM ACTIVE to PRECHARGE Command = 6 clock
> + * tRRD ACTIVE Bank A to ACTIVE Bank B Command = 2 clock
> + * tCAS CAS Latency = 3 clock
> + * tRCD SDRAM Row to Column Delay = 3 clock
> + * tRC SDRAM Row Cycle Delay = 13 clocks
> + */
> + REG ESDCFG0, 0x006ac73c
> +
> + /*
> + * Enhanced SDRAM Control Register 0
> + * Enhanced SDRAM Controller Enable = 1
> + * SDRAM Controller Operating Mode = 001 Precharge Command
> + * Supervisor Protect = 0 User mode accesses are allowed to this
> + * chip select region
> + * ROW Row Address Width. = 011 14 Row Addresses
> + * COL Column Address Width = 01 9 Col Addresses
> + * DSIZ SDRAM Memory Data Width = 00 00 16-bit memory width
> + * aligned to D[31:16]
> + * SREFR SDRAM Refresh Rate = 000 Refresh Disabled
> + * (bit field reset value)
> + * PWDT Power Down = 00 Disabled (bit field reset value) Run Mode
> + * FP Full Page = 0 0 Burst Length of the external memory device
> + * is not set to Full Page
> + * BL Burst Length = 0
> + * PRCT Precharge Timer 000000 Disabled (Bit field reset value)
> + */
> + REG ESDCTL0, 0x92200000
> + REG 0x80000f00, 0x12344321
> +
> +
> + /*
Please use tab instead of whitespace
> + * Enhanced SDRAM Control Register 0
Please use tab instead of whitespace
> + * Enhanced SDRAM Controller Enable = 1
> + * SDRAM Controller Operating Mode = 010 Auto-Refresh Command
> + * Supervisor Protect = 0 User mode accesses are allowed to this
> + * chip select region
> + * ROW Row Address Width. = 011 14 Row Addresses
> + * COL Column Address Width = 01 9 Col Addresses
> + * DSIZ SDRAM Memory Data Width = 00 00 16-bit memory width
> + * aligned to D[31:16]
> + * SREFR SDRAM Refresh Rate = 000 Refresh Disabled
> + * (bit field reset value)
> + * PWDT Power Down = 00 Disabled (bit field reset value) Run Mode
> + * FP Full Page = 0 0 Burst Length of the external memory device
> + * is not set to Full Page
> + * BL Burst Length = 0
> + * PRCT Precharge Timer 000000 Disabled (Bit field reset value)
> + */
> + REG ESDCTL0, 0xa2200000
> + REG 0x80000000, 0x12344321
> + REG 0x80000000, 0x12344321
> +
> + /*
> + * Enhanced SDRAM Control Register 0
> + * Enhanced SDRAM Controller Enable = 1
Please use tab instead of whitespace
> + * SDRAM Controller Operating Mode = 001 Precharge Command
Please use tab instead of whitespace
> + * Supervisor Protect = 0 User mode accesses are allowed to this
Please use tab instead of whitespace
> + * chip select region
> + * ROW Row Address Width. = 011 14 Row Addresses
Please use tab instead of whitespace
> + * COL Column Address Width = 01 9 Col Addresses
Please use tab instead of whitespace
> + * DSIZ SDRAM Memory Data Width = 00 00 16-bit memory width
Please use tab instead of whitespace
> + * aligned to D[31:16]
> + * SREFR SDRAM Refresh Rate = 000 Refresh Disabled
Please use tab instead of whitespace
> + * (bit field reset value)
> + * PWDT Power Down = 00 Disabled (bit field reset value) Run Mode
Please use tab instead of whitespace
> + * FP Full Page = 0 0 Burst Length of the external memory device
Please use tab instead of whitespace
> + * is not set to Full Page.
> + * BL Burst Length = 0
Please use tab instead of whitespace
> + * PRCT Precharge Timer 000000 Disabled (Bit field reset value)
Please use tab instead of whitespace
> + */
> + REG ESDCTL0, 0xb2200000
> + REG8 0x80000033, 0xda
> + REG8 0x81000000, 0xff
> +
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +
> + return 0;
> +}
> +
> +int board_init (void)
> +{
> + /* WEIM burst clock runs all the time */
> + __REG (WCR) = WCR_BCM_1;
> +
> + setup_chipselects ();
> + setup_iomux ();
> +
> + /*
> + * FIXME:
> + * Replace machine type ID by symbolic define MACH_TYPE_TQMA31 as soon
> + * as updated file mach-types.h is available in U-Boot tree.
> + * Machine type ID 1810 for TQMA31 has been registered on 2008-06-25.
> + */
> + /* Machine type ID for ARM linux */
> + gd->bd->bi_arch_number = 1810;
No please update the mach-types.h
> +
> + /* Address of boot parameters */
> + gd->bd->bi_boot_params = 0x80000100;
> +
+
> +/*
> + * Bank start addresses.
> + * 4 x 32 MiB is the maximum for user and U-Boot code. Please adapt the list
> + * as well as CFG_MAX_FLASH_BANKS to your TQM. Also consider dual die chips
> + * or single die chips, e.g. one dual die chip represents two banks.
> + */
> +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, \
Please use tab instead of whitespace
> + CFG_FLASH_BASE + 32*1024*1024, \
please add space
between operators
> + CFG_FLASH_BASE + 64*1024*1024, \
> + CFG_FLASH_BASE + 96*1024*1024}
> +
> +/* Max number of sectors on one chip */
> +#define CFG_MAX_FLASH_SECT 259
> +
> +/* Monitor at beginning of flash *
Best Regards,
J.
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