[U-Boot-Users] [PATCH v2] Add MVBC_P board
André Schwarz
Andre.Schwarz at matrix-vision.de
Tue Jul 8 20:48:43 CEST 2008
Grant Likely wrote:
> On Tue, Jul 8, 2008 at 10:16 AM, Andre Schwarz
> <andre.schwarz at matrix-vision.de> wrote:
>
>> The MVBC_P is a MPC5200B based camera system with Intel Gigabit ethernet
>> controller (using e1000) and custom Altera Cyclone-II FPGA on PCI.
>> Please see doc/README.mvbc_p for details.
>>
>> Signed-off-by: Andre Schwarz <andre.schwarz at matrix-vision.de>
>> ---
>>
>> Grant,
>>
>> I've modified the patch to meet the requested changes on the list from Kim and Wolfgang.
>> - Add MK_STR define inside header and use it for environment
>> - get rid of sync instruction by using out_* accessors
>> - get rid of various ifdefs since they are not used anyway
>> - get rid of unused function hw_watchdog_reset()
>> +static void sdram_start (int hi_addr)
>> +{
>> + long hi_bit = hi_addr ? 0x01000000 : 0;
>> +
>> + /* unlock mode register */
>> + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_bit;
>> + __asm__ volatile ("sync");
>>
>
> All of these should also use out_be32().
>
>
ok - that's "common" code on each 52xx board.
It's the same old problem that widely existing u-boot code is not
acceptable for patches ;-)
I'll fix this also - no problem.
>> +
>> + /* precharge all banks */
>> + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_bit;
>> + __asm__ volatile ("sync");
>> +
>> + /* precharge all banks */
>> + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_bit;
>> + __asm__ volatile ("sync");
>> +
>> + /* auto refresh */
>> + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_bit;
>> + __asm__ volatile ("sync");
>> +
>> + /* set mode register */
>> + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
>> + __asm__ volatile ("sync");
>> +
>> + /* normal operation */
>> + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_bit;
>> + __asm__ volatile ("sync");
>> +}
>> +
>> +phys_addr_t initdram (int board_type)
>> +{
>> + ulong dramsize = 0;
>> + ulong test1,
>> + test2;
>> +
>> + /* setup SDRAM chip selects */
>> + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;
>> + __asm__ volatile ("sync");
>>
>
> Ditto.
>
>
>> +
>> + /* setup config registers */
>> + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
>> + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
>> + __asm__ volatile ("sync");
>> +
>> + /* find RAM size using SDRAM CS0 only */
>> + sdram_start(0);
>> + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
>> + sdram_start(1);
>> + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
>> + if (test1 > test2) {
>> + sdram_start(0);
>> + dramsize = test1;
>> + } else
>> + dramsize = test2;
>> +
>> + if (dramsize < (1 << 20))
>> + dramsize = 0;
>> +
>> + /* set SDRAM CS0 size according to the amount of RAM found */
>> + if (dramsize > 0) {
>> + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
>> + __builtin_ffs(dramsize >> 20) - 1;
>> + } else {
>> + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0;
>> + }
>> + return dramsize;
>> +}
>> +
>> +void mvbc_init_gpio(void)
>> +{
>> + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
>> +
>> + printf("Ports : 0x%08x\n", gpio->port_config);
>> + printf("PORCFG: 0x%08x\n", *(vu_long*)MPC5XXX_CDM_PORCFG);
>> +
>> + out_be32(&gpio->simple_ddr, SIMPLE_DDR);
>> + out_be32(&gpio->simple_dvo, SIMPLE_DVO);
>> + out_be32(&gpio->simple_ode, SIMPLE_ODE);
>> + out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
>> +
>> + out_be32(&gpio->sint_ode, SINT_ODE);
>> + out_be32(&gpio->sint_ddr, SINT_DDR);
>> + out_be32(&gpio->sint_dvo, SINT_DVO);
>> + out_be32(&gpio->sint_inten, SINT_INTEN);
>> + out_be32(&gpio->sint_itype, SINT_ITYPE);
>> + out_be32(&gpio->sint_gpioe, SINT_GPIOEN);
>> +
>> + out_8((unsigned char *)MPC5XXX_WU_GPIO_ODE, WKUP_ODE);
>> + out_8((unsigned char *)MPC5XXX_WU_GPIO_DIR, WKUP_DIR);
>> + out_8((unsigned char *)MPC5XXX_WU_GPIO_DATA_O, WKUP_DO);
>> + out_8((unsigned char *)MPC5XXX_WU_GPIO_ENABLE, WKUP_EN);
>> +
>> + printf("simple_gpioe: 0x%08x\n", gpio->simple_gpioe);
>> + printf("sint_gpioe : 0x%08x\n", gpio->sint_gpioe);
>> +}
>> +
>> +void reset_environment(void)
>> +{
>> + char *s, sernr[64];
>> +
>> + printf("\n*** RESET ENVIRONMENT ***\n");
>> + memset(sernr, 0, sizeof(sernr));
>> + s = getenv("serial#");
>> + if (s) {
>> + printf("found serial# : %s\n", s);
>> + strncpy(sernr, s, 64);
>> + }
>> + gd->env_valid = 0;
>> + env_relocate();
>> + if (s)
>> + setenv("serial#", sernr);
>> +}
>> +
>> +int misc_init_r(void)
>> +{
>> + char *s = getenv("reset_env");
>> +
>> + if (!s) {
>> + if ((*(vu_char *)MPC5XXX_WU_GPIO_DATA_I) & WKUP_6)
>> + return 0;
>>
>
> Ditto
>
>
>> + udelay(50000);
>> + if ((*(vu_char *)MPC5XXX_WU_GPIO_DATA_I) & WKUP_6)
>> + return 0;
>> + udelay(50000);
>> + if ((*(vu_char *)MPC5XXX_WU_GPIO_DATA_I) & WKUP_6)
>> + return 0;
>> + }
>> + printf(" === FACTORY RESET ===\n");
>> + reset_environment();
>> + saveenv();
>> +
>> + return -1;
>> +}
>> +
>> +int checkboard(void)
>> +{
>> + mvbc_init_gpio();
>> + printf("Board: Matrix Vision mvBlueCOUGAR-P\n");
>> +
>> + return 0;
>> +}
>> +
>> +void flash_preinit(void)
>> +{
>> + /*
>> + * Now, when we are in RAM, enable flash write
>> + * access for detection process.
>> + * Note that CS_BOOT cannot be cleared when
>> + * executing in flash.
>> + */
>> + *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
>> +}
>> +
>> +void flash_afterinit(ulong size)
>> +{
>> + if (size == 0x800000) {
>> + *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
>> + START_REG(CFG_BOOTCS_START | size);
>> + *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
>> + STOP_REG(CFG_BOOTCS_START | size, size);
>> + }
>> +}
>> +
>> +void pci_mvbc_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
>> +{
>> + unsigned char line = 0xff;
>> + u32 base;
>> +
>> + if (PCI_BUS(dev) == 0) {
>> + switch (PCI_DEV (dev)) {
>> + case 0xa: /* FPGA */
>> + line = 3;
>> + pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &base);
>> + printf("found FPA - enable arbitration\n");
>> + *(volatile u32*)(base + 0x80c0) = cpu_to_le32(3);
>> + printf("set FPGA arbiter control : 0x%08x\n", *(volatile u32*)(base + 0x80c0));
>> + *(volatile u32*)(base + 0x8080) = cpu_to_le32(0xf0);
>> + break;
>> + case 0xb: /* LAN */
>> + line = 2;
>> + break;
>> + case 0x1a:
>> + break;
>> + default:
>> + printf ("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV (dev));
>> + break;
>> + }
>> + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line);
>> + }
>> +}
>> +
>> +struct pci_controller hose = {
>> + fixup_irq:pci_mvbc_fixup_irq
>> +};
>> +
>> +int mvbc_p_load_fpga(void)
>> +{
>> + size_t data_size = 0;
>> + void *fpga_data = NULL;
>> + char *datastr = getenv("fpgadata");
>> + char *sizestr = getenv("fpgadatasize");
>> +
>> + if (datastr)
>> + fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
>> + if (sizestr)
>> + data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
>> +
>> + return fpga_load(0, fpga_data, data_size);
>> +}
>> +
>> +extern void pci_mpc5xxx_init(struct pci_controller *);
>> +
>> +void pci_init_board(void)
>> +{
>> + char *s;
>> + int load_fpga = 1;
>> +
>> + mvbc_p_init_fpga();
>> + s = getenv("skip_fpga");
>> + if (s) {
>> + printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
>> + load_fpga = 0;
>> + }
>> + if (load_fpga) {
>> + printf("loading FPGA ... ");
>> + mvbc_p_load_fpga();
>> + printf("done\n");
>> + }
>> + pci_mpc5xxx_init(&hose);
>> +}
>> +
>> +u8 *dhcp_vendorex_prep(u8 *e)
>> +{
>> + char *ptr;
>> +
>> + /* DHCP vendor-class-identifier = 60 */
>> + if ((ptr = getenv("dhcp_vendor-class-identifier"))) {
>> + *e++ = 60;
>> + *e++ = strlen(ptr);
>> + while (*ptr)
>> + *e++ = *ptr++;
>> + }
>> + /* DHCP_CLIENT_IDENTIFIER = 61 */
>> + if ((ptr = getenv("dhcp_client_id"))) {
>> + *e++ = 61;
>> + *e++ = strlen(ptr);
>> + while (*ptr)
>> + *e++ = *ptr++;
>> + }
>> +
>> + return e;
>> +}
>> +
>> +u8 *dhcp_vendorex_proc (u8 *popt)
>> +{
>> + return NULL;
>> +}
>> +
>> +void show_boot_progress(int val)
>> +{
>> + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
>> +
>> + switch(val) {
>> + case 0: /* FPGA ok */
>> + gpio->simple_dvo |= 0x80;
>> + break;
>> + case 1:
>> + gpio->simple_dvo |= 0x40;
>> + break;
>> + case 12:
>> + gpio->simple_dvo |= 0x20;
>> + break;
>> + case 15:
>> + gpio->simple_dvo |= 0x10;
>> + break;
>> + default:
>> + break;
>> + }
>> +
>> +}
>> +
>> +void ft_board_setup(void *blob, bd_t *bd)
>> +{
>> + ft_cpu_setup(blob, bd);
>> + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
>> +}
>> diff --git a/board/mvbc_p/mvbc_p.h b/board/mvbc_p/mvbc_p.h
>> new file mode 100644
>> index 0000000..9b153e8
>> --- /dev/null
>> +++ b/board/mvbc_p/mvbc_p.h
>> @@ -0,0 +1,72 @@
>> +#ifndef __MVBC_H__
>> +#define __MVBC_H__
>> +
>> +#define SIMPLE_PSC6_3 0x20000000
>> +#define SIMPLE_PSC6_2 0x10000000
>> +#define SIMPLE_PSC3_7 0x00002000
>> +#define SIMPLE_PSC3_6 0x00001000
>> +#define SIMPLE_PSC3_3 0x00000800
>> +#define SIMPLE_PSC3_2 0x00000400
>> +#define SIMPLE_PSC3_1 0x00000200
>> +#define SIMPLE_PSC3_0 0x00000100
>> +#define SIMPLE_PSC2_3 0x00000080
>> +#define SIMPLE_PSC2_2 0x00000040
>> +#define SIMPLE_PSC2_1 0x00000020
>> +#define SIMPLE_PSC2_0 0x00000010
>> +#define SIMPLE_PSC1_3 0x00000008
>> +#define SIMPLE_PSC1_2 0x00000004
>> +#define SIMPLE_PSC1_1 0x00000002
>> +#define SIMPLE_PSC1_0 0x00000001
>> +
>> +#define SINT_PSC3_5 0x02
>> +#define SINT_PSC3_4 0x01
>> +
>> +#define WKUP_7 0x80
>> +#define WKUP_6 0x40
>> +#define WKUP_PSC6_1 0x20
>> +#define WKUP_PSC6_0 0x10
>> +#define WKUP_ETH17 0x08
>> +#define WKUP_PSC3_9 0x04
>> +#define WKUP_PSC2_4 0x02
>> +#define WKUP_PSC1_4 0x01
>> +
>>
>
> None of this looks like board specific values. Since they are MPC5200
> specific, they probably should be moved to a new file called
> include/mpc5200.h. They should also be prefixed with MPC5200_ to no
> pollute the namespace. (There is other stuff that is 5200 specific
> which should be in the same file, but I'm not asking you to do that
> also. That would be a separate activity).
>
>
ok - would you accept that ?
Mostly I touch as less common code as possible - usually it will be
rejected.
>> +#define LED_G0 SIMPLE_PSC2_0
>> +#define LED_G1 SIMPLE_PSC2_1
>> +#define LED_Y SIMPLE_PSC2_2
>> +#define LED_R SIMPLE_PSC2_3
>> +#define ARB_X_EN WKUP_PSC2_4
>> +
>> +#define FPGA_DIN SIMPLE_PSC3_0
>> +#define FPGA_CCLK SIMPLE_PSC3_1
>> +#define FPGA_CONF_DONE SIMPLE_PSC3_2
>> +#define FPGA_CONFIG SIMPLE_PSC3_3
>> +#define FPGA_STATUS SINT_PSC3_4
>> +
>> +#define MAN_RST WKUP_PSC6_0
>> +#define WD_TS WKUP_PSC6_1
>> +#define WD_WDI SIMPLE_PSC6_2
>> +#define COP_PRESENT SIMPLE_PSC6_3
>> +#define FACT_RST WKUP_6
>> +#define FLASH_RBY WKUP_7
>> +
>> +#define SIMPLE_DDR (LED_G0 | LED_G1 | LED_Y | LED_R | \
>> + FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI)
>> +#define SIMPLE_DVO (FPGA_CONFIG)
>> +#define SIMPLE_ODE (FPGA_CONFIG)
>> +#define SIMPLE_GPIOEN (LED_G0 | LED_G1 | LED_Y | LED_R | \
>> + FPGA_DIN | FPGA_CCLK | FPGA_CONF_DONE | FPGA_CONFIG |\
>> + WD_WDI | COP_PRESENT)
>> +
>> +#define SINT_ODE 0
>> +#define SINT_DDR 0
>> +#define SINT_DVO 0
>> +#define SINT_INTEN 0
>> +#define SINT_ITYPE 0
>> +#define SINT_GPIOEN (FPGA_STATUS)
>> +
>> +#define WKUP_ODE (MAN_RST)
>> +#define WKUP_DIR (ARB_X_EN|MAN_RST|WD_TS)
>> +#define WKUP_DO (ARB_X_EN|MAN_RST|WD_TS)
>> +#define WKUP_EN (ARB_X_EN|MAN_RST|WD_TS|FACT_RST|FLASH_RBY)
>> +
>> +#endif
>>
>
>
I'll send v3 tomorrow - no problem.
Thanks again for commenting.
regards,
André
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
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