[U-Boot-Users] [PATCH] Add MIMC200 board - now uses board_eth_init()

[Jean-Christophe PLAGNIOL-VILLARD]

 +
> +static const struct sdram_config sdram_config = {
> +    .data_bits    = SDRAM_DATA_16BIT,
> +    .row_bits    = 13,
> +    .col_bits    = 9,
> +    .bank_bits    = 2,
> +    .cas        = 3,
> +    .twr        = 2,
> +    .trc        = 6,
> +    .trp        = 2,
> +    .trcd        = 2,
> +    .tras        = 6,
> +    .txsr        = 6,
            ^^^^^^^^
please indent with tab for all files
> +    /* 15.6 us */
> +    .refresh_period    = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
> +};
> +
> +int board_early_init_f(void)
> +{
> +    /* Enable SDRAM in the EBI mux */
> +    hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
> +
> +    gpio_enable_ebi();
> +    gpio_enable_usart1();
> +
> +    // enable higher address lines for larger flash devices
please never use c++ comment style
> +    gpio_select_periph_A(GPIO_PIN_PE16, 0);    /* ADDR23 */
> +    gpio_select_periph_A(GPIO_PIN_PE17, 0);    /* ADDR24 */
> +    gpio_select_periph_A(GPIO_PIN_PE18, 0);    /* ADDR25 */
> +
> +    // enable data flash chip select
> +    gpio_select_periph_A(GPIO_PIN_PE25, 0);    /* NCS2 */
 +
> +    // reset phys
> +    gpio_select_pio(GPIO_PIN_PE24, 0);
> +    gpio_set_value(GPIO_PIN_PC18, 1);    /* PHY RESET    */
> +    gpio_select_pio(GPIO_PIN_PC18, GPIOF_OUTPUT);
> +
> +    // GCLK0 - 10MHz clock
> +    gpio_select_periph_A(GPIO_PIN_PA30,    0);
please replace with tab or a simple space.
> +    // GCLK1 - 25MHz clock
> +    //gpio_select_periph_A(GPIO_PIN_PA31,    0);
please remove dead code
> +
> +    udelay(5000);
> +
> +    // release phys reset
> +    gpio_set_value(GPIO_PIN_PC18, 0);    /* PHY RESET (Release)    */
> +
> +#if defined(CONFIG_MACB)
> +    gpio_enable_macb0();
> +    gpio_enable_macb1();
> +#endif
> +#if defined(CONFIG_MMC)
> +    gpio_enable_mmci();
> +#endif
> +
> +    return 0;
> +}
> +
> +phys_size_t initdram(int board_type)
> +{
> +    unsigned long expected_size;
> +    unsigned long actual_size;
> +    void *sdram_base;
> +
> +    sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
> +
> +    expected_size = sdram_init(sdram_base, &sdram_config);
> +    actual_size = get_ram_size(sdram_base, expected_size);
> +
> +    unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
> +
> +    if (expected_size != actual_size)
> +        printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
> +                actual_size >> 20, expected_size >> 20);
> +
> +    return actual_size;
> +}
> +
> +void board_init_info(void)
> +{
> +    gd->bd->bi_phy_id[0] = 0x01;
> +    gd->bd->bi_phy_id[1] = 0x03;
> +}
> +
> +/* SPI chip select control */
> +#ifdef CONFIG_ATMEL_SPI
> +#include <spi.h>
> +
> +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
> +{
> +    return bus == 0 && cs == 0;
please replace by 
	return (bus == 0) && (cs == 0);
> +}
> +
> +void spi_cs_activate(struct spi_slave *slave)
> +{
> +}
> +
> +void spi_cs_deactivate(struct spi_slave *slave)
> +{
> +}
> +#endif /* CONFIG_ATMEL_SPI */
> +
> +#ifdef CONFIG_CMD_NET
> +extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
> +
> +void board_eth_init(bd_t *bi)
> +{
> +    macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
> +    macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]);
> +}
> +#endif

> --- a/drivers/serial/atmel_usart.c
> +++ b/drivers/serial/atmel_usart.c
> @@ -21,6 +21,9 @@
> #include <asm/io.h>
> #include <asm/arch/clk.h>
> #include <asm/arch/memory-map.h>
> +#if defined(CONFIG_MIMC200_DBGLINK)
> +#include <asm/arch/gpio.h>
> +#endif
> 
> #if defined(CONFIG_USART0)
> # define USART_ID    0
> @@ -73,27 +76,67 @@ int serial_init(void)
> 
> void serial_putc(char c)
> {
> +#if defined(CONFIG_MIMC200_DBGLINK)
> +    // only output serial data if DEBUG link connected
> +    // this is connected to PIOE_21
> +    if (gpio_get_value(GPIO_PIN_PE21) == 0)
> +    {
> +#endif
> +
>     if (c == '\n')
>         serial_putc('\r');
> 
>     while (!(usart3_readl(CSR) & USART3_BIT(TXRDY))) ;
>     usart3_writel(THR, c);
> +
> +#if defined(CONFIG_MIMC200_DBGLINK)
> +    }
> +#endif
> }
> 
> void serial_puts(const char *s)
> {
> +#if defined(CONFIG_MIMC200_DBGLINK)
> +    // only output serial data if DEBUG link connected
> +    // this is connected to PIOE_21
> +    if (gpio_get_value(GPIO_PIN_PE21) == 0)
> +    {
> +#endif
> +
>     while (*s)
>         serial_putc(*s++);
> +
> +#if defined(CONFIG_MIMC200_DBGLINK)
> +    }
> +#endif
> }
> 
> int serial_getc(void)
> {
> +#if defined(CONFIG_MIMC200_DBGLINK)
> +    // only get serial data if DEBUG link connected
> +    // this is connected to PIOE_21
> +    if (gpio_get_value(GPIO_PIN_PE21) == 1)
> +    {
> +        return 0;
> +    }
> +#endif
> +
>     while (!(usart3_readl(CSR) & USART3_BIT(RXRDY))) ;
>     return usart3_readl(RHR);
> }
> 
> int serial_tstc(void)
> {
> +#if defined(CONFIG_MIMC200_DBGLINK)
> +    // only get serial data if DEBUG link connected
> +    // this is connected to PIOE_21
> +    if (gpio_get_value(GPIO_PIN_PE21) == 1)
> +    {
> +        return (1 == 0);
why not return 0?
> +    }
> +#endif
> +
>     return (usart3_readl(CSR) & USART3_BIT(RXRDY)) != 0;
> }
Could you do this with a more generic way?
Maybe not in the atmel serial.
> 
> diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h
> new file mode 100644
> index 0000000..2376a15
> --- /dev/null

Best Regards,
J.