[U-Boot-Users] [PATCH 6/7] NAND: add NAND driver for s3c64xx

[Jean-Christophe PLAGNIOL-VILLARD]

> +/*
> + * (C) Copyright 2006 DENX Software Engineering
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +
> +#include <nand.h>
> +#include <s3c6400.h>
> +
> +#include <asm/io.h>
> +
> +#ifdef CONFIG_NAND_SPL
> +#define printf(arg...) do {} while (0)
> +#endif
> +
> +/* Nand flash definition values by jsgood */
> +#define S3C_NAND_CFG_HWECC
Please move to config file
> +#undef	S3C_NAND_DEBUG
please remove
> +
> +#ifdef S3C_NAND_DEBUG
> +/*
> + * Function to print out oob buffer for debugging
> + * Written by jsgood
> + */
> +static void print_oob(const char *header, struct mtd_info *mtd)
> +{
> +	int i;
> +	struct nand_chip *chip = mtd->priv;
> +
> +	printf("%s:\t", header);
> +
> +	for(i = 0; i < 64; i++)
> +		printf("%02x ", chip->oob_poi[i]);
> +
> +	printf("\n");
> +}
> +#endif /* S3C_NAND_DEBUG */
> +
> +#ifdef CONFIG_NAND_SPL
> +static u_char nand_read_byte(struct mtd_info *mtd)
> +{
> +	struct nand_chip *this = mtd->priv;
add an empty line
> +	return readb(this->IO_ADDR_R);
> +}
> +
> +static void nand_write_byte(struct mtd_info *mtd, u_char byte)
> +{
> +	struct nand_chip *this = mtd->priv;
add an empty line
> +	writeb(byte, this->IO_ADDR_W);
> +}
> +
> +static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
> +{
> +	int i;
> +	struct nand_chip *this = mtd->priv;
> +
> +	for (i = 0; i < len; i++)
> +		buf[i] = readb(this->IO_ADDR_R);
> +}
> +#endif
> +
> +/*
> + * This function determines whether read data is good or not.
> + * If SLC, must write ecc codes to controller before reading status bit.
> + * If MLC, status bit is already set, so only reading is needed.
> + * If status bit is good, return 0.
> + * If correctable errors occured, do that.
> + * If uncorrectable errors occured, return -1.
> + * Written by jsgood
> + */
> +static int s3c_nand_correct_data(struct mtd_info *mtd, u_char *dat,
> +				 u_char *read_ecc, u_char *calc_ecc)
> +{
> +	int ret = -1;
> +	u_long nfestat0, nfmeccdata0, nfmeccdata1;
> +	u_char err_type;
> +
> +	/* SLC: Write ecc to compare */
> +	nfmeccdata0 = (calc_ecc[1] << 16) | calc_ecc[0];
> +	nfmeccdata1 = (calc_ecc[3] << 16) | calc_ecc[2];
> +	writel(nfmeccdata0, NFMECCDATA0);
> +	writel(nfmeccdata1, NFMECCDATA1);
> +
> +	/* Read ecc status */
> +	nfestat0 = readl(NFESTAT0);
> +	err_type = nfestat0 & 0x3;
> +
> +	switch (err_type) {
> +	case 0: /* No error */
> +		ret = 0;
> +		break;
> +
> +	case 1: /* 1 bit error (Correctable)
> +		   (nfestat0 >> 7) & 0x7ff	:error byte number
> +		   (nfestat0 >> 4) & 0x7	:error bit number */
> +		printf("S3C NAND: 1 bit error detected at byte %ld. Correcting from "
> +		       "0x%02x ", (nfestat0 >> 7) & 0x7ff, dat[(nfestat0 >> 7) & 0x7ff]);
> +		dat[(nfestat0 >> 7) & 0x7ff] ^= (1 << ((nfestat0 >> 4) & 0x7));
> +		printf("to 0x%02x...OK\n", dat[(nfestat0 >> 7) & 0x7ff]);
could use inline or macro to be more readable
> +		ret = 1;
> +		break;
> +
> +	case 2: /* Multiple error */
> +	case 3: /* ECC area error */
> +		printf("S3C NAND: ECC uncorrectable error detected. Not correctable.\n");
> +		ret = -1;
> +		break;
> +	}
> +
> +	return ret;
> +}
> +#endif /* S3C_NAND_CFG_HWECC */
> +
> +/*
> + * Board-specific NAND initialization. The following members of the
> + * argument are board-specific (per include/linux/mtd/nand.h):
> + * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
> + * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
> + * - hwcontrol: hardwarespecific function for accesing control-lines
> + * - dev_ready: hardwarespecific function for  accesing device ready/busy line
> + * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
> + *   only be provided if a hardware ECC is available
> + * - eccmode: mode of ecc, see defines
> + * - chip_delay: chip dependent delay for transfering data from array to
> + *   read regs (tR)
> + * - options: various chip options. They can partly be set to inform
> + *   nand_scan about special functionality. See the defines for further
> + *   explanation
> + * Members with a "?" were not set in the merged testing-NAND branch,
> + * so they are not set here either.
> + */
> +#include <linux/mtd/mtd.h>
move to the top
> +int board_nand_init(struct nand_chip *nand)
> +{
> +	NFCONT_REG 		= (NFCONT_REG & ~NFCONT_WP) | NFCONT_ENABLE | 0x6;
> +
> +	nand->IO_ADDR_R		= (void __iomem *)NFDATA;
> +	nand->IO_ADDR_W		= (void __iomem *)NFDATA;
> +	nand->hwcontrol		= s3c_nand_hwcontrol;
> +	nand->dev_ready		= s3c_nand_device_ready;
> +	nand->select_chip	= s3c_nand_select_chip;
> +	nand->options		= 0;

Best Regards,
J.