[U-Boot-Users] [Patch 13/17] U-Boot-V2:ARM:OMAP3: Add generic Headers
Sascha Hauer
s.hauer at pengutronix.de
Tue Jun 3 10:27:24 CEST 2008
On Wed, May 21, 2008 at 11:29:45AM -0500, Menon, Nishanth wrote:
> This patch adds the generic OMAP headers and OMAP specific headers.
>
> Signed-off-by: Nishanth Menon<x0nishan at ti.com>
Looks mostly ok, only one comment...
>
> ---
> include/asm-arm/arch-omap/bits.h | 65 ++++
> include/asm-arm/arch-omap/control.h | 98 ++++++
> include/asm-arm/arch-omap/gpmc.h | 105 +++++++
> include/asm-arm/arch-omap/intc.h | 58 ++++
> include/asm-arm/arch-omap/omap3-mux.h | 423 ++++++++++++++++++++++++++++++
> include/asm-arm/arch-omap/omap3-silicon.h | 130 +++++++++
> include/asm-arm/arch-omap/omap3-smx.h | 69 ++++
> include/asm-arm/arch-omap/sdrc.h | 97 ++++++
> include/asm-arm/arch-omap/silicon.h | 38 ++
> include/asm-arm/arch-omap/sys_info.h | 97 ++++++
> include/asm-arm/arch-omap/syslib.h | 39 ++
> include/asm-arm/arch-omap/timers.h | 60 ++++
> include/asm-arm/arch-omap/wdt.h | 49 +++
> 13 files changed, 1328 insertions(+)
>
> Index: u-boot-v2.git/include/asm-arm/arch-omap/bits.h
> ===================================================================
> --- /dev/null 1970-01-01 00:00:00.000000000 +0000
> +++ u-boot-v2.git/include/asm-arm/arch-omap/bits.h 2008-05-20 18:11:10.000000000 -0500
> @@ -0,0 +1,65 @@
> +/**
> + * @file
> + *
> + * @brief Provide a bunch of common BIT access macros
> + *
> + * FileName: include/asm-arm/arch-omap/bits.h
> + *
> + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz
> + */
> +/*
> + * (C) Copyright 2004-2008
> + * Texas Instruments, <www.ti.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#ifndef __ASM_OMAP_BITS_H
> +#define __ASM_OMAP_BITS_H
> +
> +#define BIT0 (1<<0)
> +#define BIT1 (1<<1)
> +#define BIT2 (1<<2)
> +#define BIT3 (1<<3)
> +#define BIT4 (1<<4)
> +#define BIT5 (1<<5)
> +#define BIT6 (1<<6)
> +#define BIT7 (1<<7)
> +#define BIT8 (1<<8)
> +#define BIT9 (1<<9)
> +#define BIT10 (1<<10)
> +#define BIT11 (1<<11)
> +#define BIT12 (1<<12)
> +#define BIT13 (1<<13)
> +#define BIT14 (1<<14)
> +#define BIT15 (1<<15)
> +#define BIT16 (1<<16)
> +#define BIT17 (1<<17)
> +#define BIT18 (1<<18)
> +#define BIT19 (1<<19)
> +#define BIT20 (1<<20)
> +#define BIT21 (1<<21)
> +#define BIT22 (1<<22)
> +#define BIT23 (1<<23)
> +#define BIT24 (1<<24)
> +#define BIT25 (1<<25)
> +#define BIT26 (1<<26)
> +#define BIT27 (1<<27)
> +#define BIT28 (1<<28)
> +#define BIT29 (1<<29)
> +#define BIT30 (1<<30)
> +#define BIT31 (1<<31)
Please don't do this. It does not really make the code shorter and every
programmer understands hwat 1<<0 means + he does not have to search
through header files for the definition of BIT0.
> +
> +#endif /*__ASM_OMAP_BITS_H */
> Index: u-boot-v2.git/include/asm-arm/arch-omap/control.h
> ===================================================================
> --- /dev/null 1970-01-01 00:00:00.000000000 +0000
> +++ u-boot-v2.git/include/asm-arm/arch-omap/control.h 2008-05-20 18:11:10.000000000 -0500
> @@ -0,0 +1,98 @@
> +/**
> + * @file
> + * @brief This file contains the Control register defines
> + *
> + * FileName: include/asm-arm/arch-omap/control.h
> + *
> + * Originally from Linux kernel:
> + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz
> + * include/asm-arm/arch-omap/omap34xx.h
> + */
> +/*
> + * (C) Copyright 2008
> + * Texas Instruments, <www.ti.com>
> + * Nishanth Menon <x0nishan at ti.com>
> + *
> + * Copyright (C) 2007 Texas Instruments, <www.ti.com>
> + * Copyright (C) 2007 Nokia Corporation.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __ASM_ARCH_OMAP_CONTROL_H
> +#define __ASM_ARCH_OMAP_CONTROL_H
> +
> +/**
> + * Control register defintion which unwraps to the real register
> + * offset + base address
> + */
> +#define CONTROL_REG(REGNAME) (OMAP_CTRL_BASE + CONTROL_##REGNAME)
> +
> +#define CONTROL_SCALABLE_OMAP_STATUS (0x44C)
> +#define CONTROL_SCALABLE_OMAP_OCP (0x534)
> +#define CONTROL_SCRATCHPAD_BASE (0x910)
> +#define CONTROL_SCRATCHPAD_ROM_BASE (0x860)
> +#define CONTROL_STATUS (0x2f0)
> +#define CONTROL_SYSCONFIG (0x010)
> +#define CONTROL_DEVCONF0 (0x274)
> +#define CONTROL_DEVCONF1 (0x2D8)
> +#define CONTROL_IVA2_BOOTMOD (0x404)
> +#define CONTROL_IVA2_BOOTADDR (0x400)
> +#define CONTROL_PBIAS_1 (0x520)
> +#define CONTROL_GENERAL_PURPOSE_STATUS (0x2F4)
> +#define CONTROL_MEM_DFTRW0 (0x278)
> +#define CONTROL_MEM_DFTRW1 (0x27C)
> +#define CONTROL_MSUSPENDMUX_0 (0x290)
> +#define CONTROL_MSUSPENDMUX_1 (0x294)
> +#define CONTROL_MSUSPENDMUX_2 (0x298)
> +#define CONTROL_MSUSPENDMUX_3 (0x29C)
> +#define CONTROL_MSUSPENDMUX_4 (0x2A0)
> +#define CONTROL_MSUSPENDMUX_5 (0x2A4)
> +#define CONTROL_SEC_CTRL (0x2B0)
> +#define CONTROL_CSIRXFE (0x2DC)
> +#define CONTROL_DEBOBS_0 (0x420)
> +#define CONTROL_DEBOBS_1 (0x424)
> +#define CONTROL_DEBOBS_2 (0x428)
> +#define CONTROL_DEBOBS_3 (0x42C)
> +#define CONTROL_DEBOBS_4 (0x430)
> +#define CONTROL_DEBOBS_5 (0x434)
> +#define CONTROL_DEBOBS_6 (0x438)
> +#define CONTROL_DEBOBS_7 (0x43C)
> +#define CONTROL_DEBOBS_8 (0x440)
> +#define CONTROL_PROG_IO0 (0x444)
> +#define CONTROL_PROG_IO1 (0x448)
> +#define CONTROL_DSS_DPLL_SPREADING (0x450)
> +#define CONTROL_CORE_DPLL_SPREADING (0x454)
> +#define CONTROL_PER_DPLL_SPREADING (0x458)
> +#define CONTROL_USBHOST_DPLL_SPREADING (0x45C)
> +#define CONTROL_TEMP_SENSOR (0x524)
> +#define CONTROL_SRAMLDO4 (0x528)
> +#define CONTROL_SRAMLDO5 (0x52C)
> +#define CONTROL_CSI (0x530)
> +#define CONTROL_SCALABLE_OMAP_OCP (0x534)
> +#define CONTROL_SCALABLE_OMAP_STATUS (0x44C)
> +
> +/** Provide the Regoffset, Value */
> +#define MUX_VAL(OFFSET,VALUE)\
> + __raw_writew((VALUE), OMAP_CTRL_BASE + (OFFSET))
> +
> +/**
> + * macro for Padconfig Registers @see
> + * include/asm/arch-arm/arch-omap/omap3-mux.h
> + */
> +#define CP(X) (CONTROL_PADCONF_##X)
> +
> +#endif /* __ASM_ARCH_OMAP_CONTROL_H */
> Index: u-boot-v2.git/include/asm-arm/arch-omap/gpmc.h
> ===================================================================
> --- /dev/null 1970-01-01 00:00:00.000000000 +0000
> +++ u-boot-v2.git/include/asm-arm/arch-omap/gpmc.h 2008-05-20 18:11:10.000000000 -0500
> @@ -0,0 +1,105 @@
> +/**
> + * @file
> + * @brief This file contains the GPMC specific register definitions
> + *
> + * FileName: include/asm-arm/arch-omap/gpmc.h
> + *
> + * Originally from Linux kernel:
> + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz
> + * include/asm-arm/arch-omap/omap34xx.h
> + */
> +/*
> + * (C) Copyright 2008
> + * Texas Instruments, <www.ti.com>
> + * Nishanth Menon <x0nishan at ti.com>
> + *
> + * Copyright (C) 2007 Texas Instruments, <www.ti.com>
> + * Copyright (C) 2007 Nokia Corporation.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __ASM_ARCH_OMAP_GPMC_H
> +#define __ASM_ARCH_OMAP_GPMC_H
> +
> +/** GPMC Reg Wrapper */
> +#define GPMC_REG(REGNAME) (OMAP_GPMC_BASE + GPMC_##REGNAME)
> +
> +#define GPMC_SYS_CONFIG (0x10)
> +#define GPMC_IRQ_ENABLE (0x1C)
> +#define GPMC_TIMEOUT_CONTROL (0x40)
> +#define GPMC_CFG (0x50)
> +#define GPMC_PREFETCH_CONFIG_1 (0x1E0)
> +#define GPMC_PREFETCH_CONFIG_2 (0x1E4)
> +#define GPMC_PREFETCH_CTRL (0x1EC)
> +#define GPMC_CONFIG1_0 (0x60)
> +#define GPMC_CONFIG1_1 (0x90)
> +#define GPMC_CONFIG1_2 (0xC0)
> +#define GPMC_CONFIG1_3 (0xF0)
> +#define GPMC_CONFIG1_4 (0x120)
> +#define GPMC_CONFIG1_5 (0x150)
> +#define GPMC_CONFIG1_6 (0x180)
> +#define GPMC_CONFIG1_7 (0x1B0)
> +#define GPMC_CONFIG2_0 (0x64)
> +#define GPMC_CONFIG2_1 (0x94)
> +#define GPMC_CONFIG2_2 (0xC4)
> +#define GPMC_CONFIG2_3 (0xF4)
> +#define GPMC_CONFIG2_4 (0x124)
> +#define GPMC_CONFIG2_5 (0x154)
> +#define GPMC_CONFIG2_6 (0x184)
> +#define GPMC_CONFIG2_7 (0x1B4)
> +#define GPMC_CONFIG3_0 (0x68)
> +#define GPMC_CONFIG3_1 (0x98)
> +#define GPMC_CONFIG3_2 (0xC8)
> +#define GPMC_CONFIG3_3 (0xF8)
> +#define GPMC_CONFIG3_4 (0x128)
> +#define GPMC_CONFIG3_5 (0x158)
> +#define GPMC_CONFIG3_6 (0x188)
> +#define GPMC_CONFIG3_7 (0x1B8)
> +#define GPMC_CONFIG4_0 (0x6C)
> +#define GPMC_CONFIG4_1 (0x9C)
> +#define GPMC_CONFIG4_2 (0xCC)
> +#define GPMC_CONFIG4_3 (0xFC)
> +#define GPMC_CONFIG4_4 (0x12C)
> +#define GPMC_CONFIG4_5 (0x15C)
> +#define GPMC_CONFIG4_6 (0x18C)
> +#define GPMC_CONFIG4_7 (0x1BC)
> +#define GPMC_CONFIG5_0 (0x70)
> +#define GPMC_CONFIG5_1 (0xA0)
> +#define GPMC_CONFIG5_2 (0xD0)
> +#define GPMC_CONFIG5_3 (0x100)
> +#define GPMC_CONFIG5_4 (0x130)
> +#define GPMC_CONFIG5_5 (0x160)
> +#define GPMC_CONFIG5_6 (0x190)
> +#define GPMC_CONFIG5_7 (0x1C0)
> +#define GPMC_CONFIG6_0 (0x74)
> +#define GPMC_CONFIG6_1 (0xA4)
> +#define GPMC_CONFIG6_2 (0xD4)
> +#define GPMC_CONFIG6_3 (0x104)
> +#define GPMC_CONFIG6_4 (0x134)
> +#define GPMC_CONFIG6_5 (0x164)
> +#define GPMC_CONFIG6_6 (0x194)
> +#define GPMC_CONFIG6_7 (0x1C4)
> +#define GPMC_CONFIG7_0 (0x78)
> +#define GPMC_CONFIG7_1 (0xA8)
> +#define GPMC_CONFIG7_2 (0xD8)
> +#define GPMC_CONFIG7_3 (0x108)
> +#define GPMC_CONFIG7_4 (0x138)
> +#define GPMC_CONFIG7_5 (0x168)
> +#define GPMC_CONFIG7_6 (0x198)
> +#define GPMC_CONFIG7_7 (0x1C8)
> +
> +#endif /* __ASM_ARCH_OMAP_GPMC_H */
> Index: u-boot-v2.git/include/asm-arm/arch-omap/intc.h
> ===================================================================
> --- /dev/null 1970-01-01 00:00:00.000000000 +0000
> +++ u-boot-v2.git/include/asm-arm/arch-omap/intc.h 2008-05-20 18:11:10.000000000 -0500
> @@ -0,0 +1,58 @@
> +/**
> + * @file
> + * @brief This file contains the Interrupt controller register defines
> + *
> + * FileName: include/asm-arm/arch-omap/intc.h
> + *
> + * Originally from Linux kernel:
> + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz
> + * include/asm-arm/arch-omap/omap34xx.h
> + */
> +/*
> + * (C) Copyright 2008
> + * Texas Instruments, <www.ti.com>
> + * Nishanth Menon <x0nishan at ti.com>
> + *
> + * Copyright (C) 2007 Texas Instruments, <www.ti.com>
> + * Copyright (C) 2007 Nokia Corporation.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __ASM_ARCH_OMAP_INTC_H
> +#define __ASM_ARCH_OMAP_INTC_H
> +
> +/** Interrupt Controller Register wrapper */
> +#define INTC_REG(REGNAME) (OMAP_INTC_BASE + INTC_##REGNAME)
> +
> +#define INTC_MIR_0 (0x084)
> +#define INTC_MIR_1 (0x0A4)
> +#define INTC_MIR_2 (0x0C4)
> +#define INTC_MIR_SET_0 (0x08C)
> +#define INTC_MIR_SET_1 (0x0AC)
> +#define INTC_MIR_SET_2 (0x0CC)
> +#define INTC_MIR_CLEAR_0 (0x094)
> +#define INTC_MIR_CLEAR_1 (0x0B4)
> +#define INTC_MIR_CLEAR_2 (0x0D4)
> +#define INTC_PS_SYSCONFIG (0x010)
> +#define INTC_PS_PROTECTION (0x04C)
> +#define INTC_PS_IDLE (0x050)
> +#define INTC_PS_THRESHOLD (0x068)
> +#define INTC_PS_PENDING_IRQ0 (0x098)
> +#define INTC_PS_PENDING_IRQ1 (0x0B8)
> +#define INTC_PS_PENDING_IRQ2 (0x0D8)
> +
> +#endif /* __ASM_ARCH_OMAP_INTC_H */
> Index: u-boot-v2.git/include/asm-arm/arch-omap/omap3-silicon.h
> ===================================================================
> --- /dev/null 1970-01-01 00:00:00.000000000 +0000
> +++ u-boot-v2.git/include/asm-arm/arch-omap/omap3-silicon.h 2008-05-20 18:11:10.000000000 -0500
> @@ -0,0 +1,130 @@
> +/**
> + * @file
> + * @brief This file contains the processor specific definitions of
> + * the TI OMAP34XX. For more info on OMAP34XX,
> + * See http://focus.ti.com/pdfs/wtbu/swpu114g.pdf
> + *
> + * FileName: include/asm-arm/arch-omap/omap3-silicon.h
> + *
> + * OMAP34XX base address defines go here.
> + *
> + * Originally from Linux kernel:
> + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz
> + * include/asm-arm/arch-omap/omap3-silicon.h
> + */
> +/*
> + * (C) Copyright 2008
> + * Texas Instruments, <www.ti.com>
> + * Nishanth Menon <x0nishan at ti.com>
> + *
> + * Copyright (C) 2007 Texas Instruments, <www.ti.com>
> + * Copyright (C) 2007 Nokia Corporation.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __ASM_ARCH_OMAP3_H
> +#define __ASM_ARCH_OMAP3_H
> +
> +/* PLEASE PLACE ONLY BASE DEFINES HERE */
> +
> +/** OMAP Internal Bus Base addresses */
> +#define OMAP_L4_CORE_BASE 0x48000000
> +#define OMAP_INTC_BASE 0x48200000
> +#define OMAP_L4_WKUP_BASE 0x48300000
> +#define OMAP_L4_PER_BASE 0x49000000
> +#define OMAP_L4_EMU_BASE 0x54000000
> +#define OMAP_SGX_BASE 0x50000000
> +#define OMAP_IVA_BASE 0x5C000000
> +#define OMAP_SMX_APE_BASE 0x68000000
> +#define OMAP_SMS_BASE 0x6C000000
> +#define OMAP_SDRC_BASE 0x6D000000
> +#define OMAP_GPMC_BASE 0x6E000000
> +
> +/** Peripheral Base Addresses */
> +#define OMAP_CTRL_BASE (OMAP_L4_CORE_BASE + 0x02000)
> +#define OMAP_CM_BASE (OMAP_L4_CORE_BASE + 0x04000)
> +#define OMAP_PRM_BASE (OMAP_L4_WKUP_BASE + 0x06000)
> +
> +#define OMAP_UART1_BASE (OMAP_L4_CORE_BASE + 0x6A000)
> +#define OMAP_UART2_BASE (OMAP_L4_CORE_BASE + 0x6C000)
> +#define OMAP_UART3_BASE (OMAP_L4_PER_BASE + 0x20000)
> +
> +#define OMAP_I2C1_BASE (OMAP_L4_CORE_BASE + 0x70000)
> +#define OMAP_I2C2_BASE (OMAP_L4_CORE_BASE + 0x72000)
> +#define OMAP_I2C3_BASE (OMAP_L4_CORE_BASE + 0x60000)
> +
> +#define OMAP_GPTIMER1_BASE (OMAP_L4_WKUP_BASE + 0x18000)
> +#define OMAP_GPTIMER2_BASE (OMAP_L4_PER_BASE + 0x32000)
> +#define OMAP_GPTIMER3_BASE (OMAP_L4_PER_BASE + 0x34000)
> +#define OMAP_GPTIMER4_BASE (OMAP_L4_PER_BASE + 0x36000)
> +#define OMAP_GPTIMER5_BASE (OMAP_L4_PER_BASE + 0x38000)
> +#define OMAP_GPTIMER6_BASE (OMAP_L4_PER_BASE + 0x3A000)
> +#define OMAP_GPTIMER7_BASE (OMAP_L4_PER_BASE + 0x3C000)
> +#define OMAP_GPTIMER8_BASE (OMAP_L4_PER_BASE + 0x3E000)
> +#define OMAP_GPTIMER9_BASE (OMAP_L4_PER_BASE + 0x40000)
> +#define OMAP_GPTIMER10_BASE (OMAP_L4_CORE_BASE + 0x86000)
> +#define OMAP_GPTIMER11_BASE (OMAP_L4_CORE_BASE + 0x88000)
> +
> +#define OMAP_WDTIMER2_BASE (OMAP_L4_WKUP_BASE + 0x14000)
> +#define OMAP_WDTIMER3_BASE (OMAP_L4_PER_BASE + 0x30000)
> +
> +#define OMAP_32KTIMER_BASE (OMAP_L4_WKUP_BASE + 0x20000)
> +
> +#define OMAP_MMC1_BASE (OMAP_L4_CORE_BASE + 0x9C000)
> +#define OMAP_MMC2_BASE (OMAP_L4_CORE_BASE + 0xB4000)
> +#define OMAP_MMC3_BASE (OMAP_L4_CORE_BASE + 0xAD000)
> +
> +#define OMAP_MUSB0_BASE (OMAP_L4_CORE_BASE + 0xAB000)
> +
> +#define OMAP_GPIO1_BASE (OMAP_L4_WKUP_BASE + 0x10000)
> +#define OMAP_GPIO2_BASE (OMAP_L4_PER_BASE + 0x50000)
> +#define OMAP_GPIO3_BASE (OMAP_L4_PER_BASE + 0x52000)
> +#define OMAP_GPIO4_BASE (OMAP_L4_PER_BASE + 0x54000)
> +#define OMAP_GPIO5_BASE (OMAP_L4_PER_BASE + 0x56000)
> +#define OMAP_GPIO6_BASE (OMAP_L4_PER_BASE + 0x58000)
> +
> +/** MPU WDT Definition */
> +#define OMAP_MPU_WDTIMER_BASE OMAP_WDTIMER2_BASE
> +
> +/** Interrupt Vector base address */
> +#define OMAP_SRAM_INTVECT 0x4020F800
> +#define OMAP_SRAM_INTVECT_COPYSIZE 0x64
> +/** Temporary stack for us to use C calls in low_level_init */
> +#define OMAP_SRAM_STACK 0x4020FFFC
> +
> +/** Gives the silicon revision */
> +#define OMAP_TAP_BASE (OMAP_L4_WKUP_BASE + 0xA000)
> +#define IDCODE_REG (OMAP_TAP_BASE + 0x204)
> +
> +/************ Generic Chip specific Definitions **********/
> +/**
> + * CHIP F number HAWKEYE (hex)
> + * OMAP3430 ES1.0 F771609 B6D6
> + * OMAP3430 ES2.0 F771609A B7AE
> + */
> +#define HAWKEYE_ES1 0x0B6D6000
> +#define HAWKEYE_ES2 0x0B7AE000
> +#define HAWKEYE_ES2_1 0x1B7AE000
> +#define HAWKEYE_MASK 0x0FFFF000
> +#define VERSION_MASK 0xF0000000
> +#define DEVICE_MASK (BIT8|BIT9|BIT10)
> +
> +#define OMAP_SDRC_CS0 0x80000000
> +#define OMAP_SDRC_CS1 0xA0000000
> +
> +#endif /* __ASM_ARCH_OMAP3_H */
> +
> Index: u-boot-v2.git/include/asm-arm/arch-omap/omap3-smx.h
> ===================================================================
> --- /dev/null 1970-01-01 00:00:00.000000000 +0000
> +++ u-boot-v2.git/include/asm-arm/arch-omap/omap3-smx.h 2008-05-20 18:11:10.000000000 -0500
> @@ -0,0 +1,69 @@
> +/**
> + * @file
> + * @brief This file contains the SMX specific register definitions
> + *
> + * FileName: include/asm-arm/arch-omap/omap3-smx.h
> + *
> + * Originally from Linux kernel:
> + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz
> + * include/asm-arm/arch-omap/omap34xx.h
> + */
> +/*
> + * (C) Copyright 2008
> + * Texas Instruments, <www.ti.com>
> + * Nishanth Menon <x0nishan at ti.com>
> + *
> + * Copyright (C) 2007 Texas Instruments, <www.ti.com>
> + * Copyright (C) 2007 Nokia Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> + */
> +
> +#ifndef __ASM_ARCH_OMAP_SMX_H
> +#define __ASM_ARCH_OMAP_SMX_H
> +
> +/* SMX-APE */
> +#define PM_RT_APE_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x10000)
> +#define PM_GPMC_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x12400)
> +#define PM_OCM_RAM_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x12800)
> +#define PM_OCM_ROM_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x12C00)
> +#define PM_IVA2_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x14000)
> +
> +#define RT_REQ_INFO_PERMISSION_1 (PM_RT_APE_BASE_ADDR_ARM + 0x68)
> +#define RT_READ_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x50)
> +#define RT_WRITE_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x58)
> +#define RT_ADDR_MATCH_1 (PM_RT_APE_BASE_ADDR_ARM + 0x60)
> +
> +#define GPMC_REQ_INFO_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x48)
> +#define GPMC_READ_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x50)
> +#define GPMC_WRITE_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x58)
> +
> +#define OCM_REQ_INFO_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x48)
> +#define OCM_READ_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x50)
> +#define OCM_WRITE_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x58)
> +#define OCM_ADDR_MATCH_2 (PM_OCM_RAM_BASE_ADDR_ARM + 0x80)
> +
> +/* IVA2 */
> +#define IVA2_REQ_INFO_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x48)
> +#define IVA2_READ_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x50)
> +#define IVA2_WRITE_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x58)
> +
> +/* SMS */
> +#define SMS_SYSCONFIG (OMAP_SMS_BASE + 0x10)
> +#define SMS_RG_ATT0 (OMAP_SMS_BASE + 0x48)
> +#define SMS_CLASS_ARB0 (OMAP_SMS_BASE + 0xD0)
> +#define BURSTCOMPLETE_GROUP7 BIT31
> +
> +#endif /* __ASM_ARCH_OMAP_SMX_H */
> Index: u-boot-v2.git/include/asm-arm/arch-omap/sdrc.h
> ===================================================================
> --- /dev/null 1970-01-01 00:00:00.000000000 +0000
> +++ u-boot-v2.git/include/asm-arm/arch-omap/sdrc.h 2008-05-20 18:11:10.000000000 -0500
> @@ -0,0 +1,97 @@
> +/**
> + * @file
> + * @brief This file contains the SDRC specific register definitions
> + *
> + * FileName: include/asm-arm/arch-omap/sdrc.h
> + *
> + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz
> + */
> +/*
> + * (C) Copyright 2006-2008
> + * Texas Instruments, <www.ti.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + *
> + */
> +
> +#ifndef _ASM_ARCH_SDRC_H
> +#define _ASM_ARCH_SDRC_H
> +
> +#define SDRC_REG(REGNAME) (OMAP_SDRC_BASE + OMAP_SDRC_##REGNAME)
> +#define OMAP_SDRC_SYSCONFIG (0x10)
> +#define OMAP_SDRC_STATUS (0x14)
> +#define OMAP_SDRC_CS_CFG (0x40)
> +#define OMAP_SDRC_SHARING (0x44)
> +#define OMAP_SDRC_DLLA_CTRL (0x60)
> +#define OMAP_SDRC_DLLA_STATUS (0x64)
> +#define OMAP_SDRC_DLLB_CTRL (0x68)
> +#define OMAP_SDRC_DLLB_STATUS (0x6C)
> +#define DLLPHASE BIT1
> +#define LOADDLL BIT2
> +#define DLL_DELAY_MASK 0xFF00
> +#define DLL_NO_FILTER_MASK (BIT8|BIT9)
> +
> +#define OMAP_SDRC_POWER (0x70)
> +#define WAKEUPPROC BIT26
> +
> +#define OMAP_SDRC_MCFG_0 (0x80)
> +#define OMAP_SDRC_MCFG_1 (0xB0)
> +#define OMAP_SDRC_MR_0 (0x84)
> +#define OMAP_SDRC_MR_1 (0xB4)
> +#define OMAP_SDRC_ACTIM_CTRLA_0 (0x9C)
> +#define OMAP_SDRC_ACTIM_CTRLB_0 (0xA0)
> +#define OMAP_SDRC_ACTIM_CTRLA_1 (0xC4)
> +#define OMAP_SDRC_ACTIM_CTRLB_1 (0xC8)
> +#define OMAP_SDRC_RFR_CTRL_0 (0xA4)
> +#define OMAP_SDRC_RFR_CTRL_1 (0xD4)
> +#define OMAP_SDRC_MANUAL_0 (0xA8)
> +#define CMD_NOP 0x0
> +#define CMD_PRECHARGE 0x1
> +#define CMD_AUTOREFRESH 0x2
> +#define CMD_ENTR_PWRDOWN 0x3
> +#define CMD_EXIT_PWRDOWN 0x4
> +#define CMD_ENTR_SRFRSH 0x5
> +#define CMD_CKE_HIGH 0x6
> +#define CMD_CKE_LOW 0x7
> +#define SOFTRESET BIT1
> +#define SMART_IDLE (0x2 << 3)
> +#define REF_ON_IDLE (0x1 << 6)
> +
> +#define SDRC_CS0_OSET 0x0
> +/* Mirror CS1 regs appear offset 0x30 from CS0 */
> +#define SDRC_CS1_OSET 0x30
> +
> +#define SDRC_STACKED 0
> +#define SDRC_IP_DDR 1
> +#define SDRC_COMBO_DDR 2
> +#define SDRC_IP_SDR 3
> +
> +
> +#define SDRC_B_R_C (0 << 6) /* bank-row-column */
> +#define SDRC_B1_R_B0_C (1 << 6) /* bank1-row-bank0-column */
> +#define SDRC_R_B_C (2 << 6) /* row-bank-column */
> +
> +#define DLL_OFFSET 0
> +#define DLL_WRITEDDRCLKX2DIS 1
> +#define DLL_ENADLL 1
> +#define DLL_LOCKDLL 0
> +#define DLL_DLLPHASE_72 0
> +#define DLL_DLLPHASE_90 1
> +
> +#endif /* _ASM_ARCH_SDRC_H */
> Index: u-boot-v2.git/include/asm-arm/arch-omap/silicon.h
> ===================================================================
> --- /dev/null 1970-01-01 00:00:00.000000000 +0000
> +++ u-boot-v2.git/include/asm-arm/arch-omap/silicon.h 2008-05-20 18:11:10.000000000 -0500
> @@ -0,0 +1,38 @@
> +/*
> + * (C) Copyright 2008
> + * Texas Instruments, <www.ti.com>
> + * Nishanth Menon <x0nishan at ti.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#ifndef __ASM_ARCH_OMAP_SILICON_H
> +#define __ASM_ARCH_OMAP_SILICON_H
> +
> +#include <asm/arch/bits.h>
> +
> +/* Each platform silicon header comes here */
> +#ifdef CONFIG_ARCH_OMAP3
> +#include <asm/arch/omap3-silicon.h>
> +#endif
> +
> +/* If Architecture specific init functions are present */
> +#ifdef CONFIG_ARCH_HAS_LOWLEVEL_INIT
> +#ifndef __ASSEMBLY__
> +void a_init(void);
> +#endif /* __ASSEMBLY__ */
> +#endif
> +
> +#endif /* __ASM_ARCH_OMAP_SILICON_H */
> Index: u-boot-v2.git/include/asm-arm/arch-omap/sys_info.h
> ===================================================================
> --- /dev/null 1970-01-01 00:00:00.000000000 +0000
> +++ u-boot-v2.git/include/asm-arm/arch-omap/sys_info.h 2008-05-20 18:11:10.000000000 -0500
> @@ -0,0 +1,97 @@
> +/**
> + * @file
> + * @brief This file defines the macros apis which are useful for most OMAP
> + * platforms.
> + *
> + * FileName: include/asm-arm/arch-omap/sys_info.h
> + *
> + * These are implemented by the System specific code in omapX-generic.c
> + *
> + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz
> + */
> +/*
> + * (C) Copyright 2006-2008
> + * Texas Instruments, <www.ti.com>
> + * Richard Woodruff <r-woodruff2 at ti.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __ASM_ARCH_SYS_INFO_H_
> +#define __ASM_ARCH_SYS_INFO_H_
> +
> +#define XDR_POP 5 /* package on package part */
> +#define SDR_DISCRETE 4 /* 128M memory SDR module*/
> +#define DDR_STACKED 3 /* stacked part on 2422 */
> +#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */
> +#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */
> +
> +#define DDR_100 100 /* type found on most mem d-boards */
> +#define DDR_111 111 /* some combo parts */
> +#define DDR_133 133 /* most combo, some mem d-boards */
> +#define DDR_165 165 /* future parts */
> +
> +#define CPU_3430 0x3430
> +#define CPU_2430 0x2430
> +#define CPU_2420 0x2420
> +#define CPU_1710 0x1710
> +#define CPU_1610 0x1610
> +
> +/**
> + * CPU revision
> + */
> +#define CPU_ES1 1
> +#define CPU_ES1P1 2
> +#define CPU_ES1P2 3
> +#define CPU_ES2 4
> +#define CPU_ES2P1 5
> +#define CPU_ES2P2 6
> +#define CPU_ES3 7
> +#define CPU_ES3P1 8
> +#define CPU_ES3P2 9
> +#define CPU_ES4 10
> +#define CPU_ES4P1 11
> +#define CPU_ES4P2 12
> +
> +#define GPMC_MUXED 1
> +#define GPMC_NONMUXED 0
> +
> +#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */
> +#define TYPE_NOR 0x000
> +#define TYPE_ONENAND 0x800
> +
> +#define WIDTH_8BIT 0x0000
> +#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
> +
> +#define TST_DEVICE 0x0
> +#define EMU_DEVICE 0x1
> +#define HS_DEVICE 0x2
> +#define GP_DEVICE 0x3
> +
> +/** These are implemented by the System specific code in omapX-generic.c */
> +u32 get_cpu_type(void);
> +u32 get_cpu_rev(void);
> +u32 get_sdr_cs_size(u32 offset);
> +inline u32 get_sysboot_value(void);
> +u32 get_gpmc0_base(void);
> +u32 get_base(void);
> +u32 running_in_flash(void);
> +u32 running_in_sram(void);
> +u32 running_in_sdram(void);
> +u32 get_boot_type(void);
> +u32 get_device_type(void);
> +
> +#endif /*__ASM_ARCH_SYS_INFO_H_ */
> Index: u-boot-v2.git/include/asm-arm/arch-omap/syslib.h
> ===================================================================
> --- /dev/null 1970-01-01 00:00:00.000000000 +0000
> +++ u-boot-v2.git/include/asm-arm/arch-omap/syslib.h 2008-05-20 18:11:10.000000000 -0500
> @@ -0,0 +1,39 @@
> +/**
> + * @file
> + * @brief These Apis are OMAP independent support functions
> + *
> + * FileName: include/asm-arm/arch-omap/syslib.h
> + *
> + * Implemented by arch/arm/mach-omap/syslib.c
> + *
> + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz
> + */
> +/*
> + * (C) Copyright 2004-2008
> + * Texas Instruments, <www.ti.com>
> + * Richard Woodruff <r-woodruff2 at ti.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#ifndef __ASM_ARCH_OMAP_SYSLIB_H_
> +#define __ASM_ARCH_OMAP_SYSLIB_H_
> +
> +/** System Independent functions */
> +void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value);
> +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound);
> +void sdelay(unsigned long loops);
> +
> +#endif /* __ASM_ARCH_OMAP_SYSLIB_H_ */
> Index: u-boot-v2.git/include/asm-arm/arch-omap/timers.h
> ===================================================================
> --- /dev/null 1970-01-01 00:00:00.000000000 +0000
> +++ u-boot-v2.git/include/asm-arm/arch-omap/timers.h 2008-05-20 18:11:10.000000000 -0500
> @@ -0,0 +1,60 @@
> +/**
> + * @file
> + * @brief This defines the Register defines for OMAP GPTimers and Sync32 timers.
> + *
> + * FileName: include/asm-arm/arch-omap/timers.h
> + *
> + * Originally from Linux kernel:
> + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz
> + *
> + */
> +/*
> + * (C) Copyright 2008
> + * Texas Instruments, <www.ti.com>
> + * Nishanth Menon <x0nishan at ti.com>
> + *
> + * Copyright (C) 2007 Texas Instruments, <www.ti.com>
> + * Copyright (C) 2007 Nokia Corporation.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#ifndef __ASM_ARCH_GPT_H
> +#define __ASM_ARCH_GPT_H
> +
> +/** General Purpose timer regs offsets (32 bit regs) */
> +#define TIDR 0x0 /* r */
> +#define TIOCP_CFG 0x10 /* rw */
> +#define TISTAT 0x14 /* r */
> +#define TISR 0x18 /* rw */
> +#define TIER 0x1C /* rw */
> +#define TWER 0x20 /* rw */
> +#define TCLR 0x24 /* rw */
> +#define TCRR 0x28 /* rw */
> +#define TLDR 0x2C /* rw */
> +#define TTGR 0x30 /* rw */
> +#define TWPS 0x34 /* r */
> +#define TMAR 0x38 /* rw */
> +#define TCAR1 0x3c /* r */
> +#define TSICR 0x40 /* rw */
> +#define TCAR2 0x44 /* r */
> +/* Enable sys_clk NO-prescale /1 */
> +#define GPT_EN ((0<<2) | BIT1 | BIT0)
> +
> +/** Sync 32Khz Timer registers */
> +#define S32K_CR (OMAP_32KTIMER_BASE + 0x10)
> +#define S32K_FREQUENCY 32768
> +
> +#endif /*__ASM_ARCH_GPT_H */
> Index: u-boot-v2.git/include/asm-arm/arch-omap/wdt.h
> ===================================================================
> --- /dev/null 1970-01-01 00:00:00.000000000 +0000
> +++ u-boot-v2.git/include/asm-arm/arch-omap/wdt.h 2008-05-20 18:11:10.000000000 -0500
> @@ -0,0 +1,49 @@
> +/**
> + * @file
> + * @brief This file contains the Watchdog timer specific register definitions
> + *
> + * FileName: include/asm-arm/arch-omap/wdt.h
> + *
> + */
> +/*
> + * (C) Copyright 2008
> + * Texas Instruments, <www.ti.com>
> + * Nishanth Menon <x0nishan at ti.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#ifndef __ASM_ARCH_OMAP_WDT_H
> +#define __ASM_ARCH_OMAP_WDT_H
> +
> +/** Watchdog Register defines */
> +#define WDT_REG(REGNAME) (OMAP_MPU_WDTIMER_BASE + OMAP_WDT_##REGNAME)
> +#define OMAP_WDT_WIDR (0x000)
> +#define OMAP_WDT_SYSCONFIG (0x010)
> +#define OMAP_WDT_WD_SYSSTATUS (0x014)
> +#define OMAP_WDT_WISR (0x018)
> +#define OMAP_WDT_WIER (0x01C)
> +#define OMAP_WDT_WCLR (0x024)
> +#define OMAP_WDT_WCRR (0x028)
> +#define OMAP_WDT_WLDR (0x02C)
> +#define OMAP_WDT_WTGR (0x030)
> +#define OMAP_WDT_WWPS (0x034)
> +#define OMAP_WDT_WSPR (0x048)
> +
> +/* Unlock Code for Watchdog timer to disable the same */
> +#define WDT_DISABLE_CODE1 0xAAAA
> +#define WDT_DISABLE_CODE2 0x5555
> +
> +#endif /* __ASM_ARCH_OMAP_WDT_H */
>
--
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