[U-Boot-Users] [PATCH] 85xx: Add setting of cache props in the device tree.
Kumar Gala
galak at kernel.crashing.org
Wed Jun 4 05:11:04 CEST 2008
On Jun 3, 2008, at 7:35 PM, Andy Fleming wrote:
> On Thu, May 29, 2008 at 11:22 AM, Kumar Gala <galak at kernel.crashing.org
> > wrote:
>> Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
>> ---
>> cpu/mpc85xx/fdt.c | 128 +++++++++++++++++++++++++++++++++++++++++++
>> ++++++++++
>> 1 files changed, 128 insertions(+), 0 deletions(-)
>>
>> diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
>> index bb87740..92952e6 100644
>> --- a/cpu/mpc85xx/fdt.c
>> +++ b/cpu/mpc85xx/fdt.c
>> @@ -26,6 +26,7 @@
>> #include <common.h>
>> #include <libfdt.h>
>> #include <fdt_support.h>
>> +#include <asm/processor.h>
>>
>> extern void ft_qe_setup(void *blob);
>> #ifdef CONFIG_MP
>> @@ -77,6 +78,131 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
>> }
>> #endif
>>
>> +#ifdef CONFIG_L2_CACHE
>> +/* return size in kilobytes */
>> +static inline u32 l2cache_size(void)
>> +{
>> + volatile ccsr_l2cache_t *l2cache = (void
>> *)CFG_MPC85xx_L2_ADDR;
>> + volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
>> + u32 ver = SVR_SOC_VER(get_svr());
>> +
>> + switch (l2siz_field) {
>> + case 0x0:
>> + break;
>> + case 0x1:
>> + if (ver == SVR_8540 || ver == SVR_8560 ||
>> + ver == SVR_8541 || ver == SVR_8541_E ||
>> + ver == SVR_8555 || ver == SVR_8555_E)
>> + return 128;
>> + else
>> + return 256;
>> + break;
>> + case 0x2:
>> + if (ver == SVR_8540 || ver == SVR_8560 ||
>> + ver == SVR_8541 || ver == SVR_8541_E ||
>> + ver == SVR_8555 || ver == SVR_8555_E)
>> + return 256;
>> + else
>> + return 512;
>> + break;
>> + case 0x3:
>> + return 1024;
>> + break;
>> + }
>> +
>> + return 0;
>> +}
>
> How about we create a feature in the new cpu_type field you created,
> and use that to flag it. :)
Seems overkill for such a small difference and one that is just for
the "e500v1" generation of 85xx chips.
- k
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