[U-Boot-Users] [Patch 10/17 Try 2] U-Boot-V2:ARM:OMAP3: Add support for OMAP and Cortex A8
Menon, Nishanth
x0nishan at ti.com
Wed Jun 4 07:06:26 CEST 2008
Sascha,
> -----Original Message-----
> From: Menon, Nishanth
> Sent: Tuesday, June 03, 2008 10:38 AM
> To: 'Laurent Desnogues'; u-boot-users at lists.sourceforge.net; dirk.behme at googlemail.com;
> philip.balister at gmail.com; Gopinath, Thara; Kamat, Nishant; Syed Mohammed, Khasim
> Subject: RE: [Patch 10/17] U-Boot-V2:ARM:OMAP3: Add support for OMAP and Cortex A8
>
> > -----Original Message-----
> > From: Laurent Desnogues [mailto:laurent.desnogues at gmail.com]
> > Sent: Tuesday, June 03, 2008 3:23 AM
> > To: Menon, Nishanth; u-boot-users at lists.sourceforge.net; Laurent Desnogues;
> > dirk.behme at googlemail.com; philip.balister at gmail.com; Gopinath, Thara; Kamat, Nishant; Syed
> > Subject: Re: [Patch 10/17] U-Boot-V2:ARM:OMAP3: Add support for OMAP and Cortex A8
> >
> > On Tue, Jun 3, 2008 at 10:12 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> > > Is this really ARMCORTEX specific or arm v7 specific?
> >
> > This is not Cortex A8 specific, it's v7-A (and hopefully will be the same
> > in upcoming ARM architectures).
> Probably ARM arch definitions need to be cleaned up a bit more? Granularity is restricted today to
> ARM CPU and not architecture..
>
> >
> > > Anyway, this looks
> > > like the start of another ifdef mess, we should create some generic hook
> > > here.
> >
> > You could perhaps mimic the way the Linux kernel handles cache stuff
> > for the various ARM architectures.
> Probably not the extent.. but yes to a lesser extent might be helpful. Common code will still exist,
> probably CP15 stuff can move out?
Keeping the current code, but resyncing based on MALLOC changes. Need clean up of ARM proc specific changes pretty soon I guess. ARMV4, V6, V7 support to be independent of common code.
Signed-off-by: Nishanth Menon<x0nishan at ti.com>
---
arch/arm/Kconfig | 23 +++++++++++++++++++-
arch/arm/Makefile | 6 +++++
arch/arm/cpu/Makefile | 1
arch/arm/cpu/start-arm.S | 54 +++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 83 insertions(+), 1 deletion(-)
Index: u-boot.v2/arch/arm/Kconfig
===================================================================
--- u-boot.v2.orig/arch/arm/Kconfig 2008-06-03 20:27:47.000000000 -0500
+++ u-boot.v2/arch/arm/Kconfig 2008-06-03 20:45:08.000000000 -0500
@@ -47,6 +47,9 @@
config ARM926EJS
bool
+config ARMCORTEXA8
+ bool
+
# i.MX1, i.MXL, i.MX27 and i.MX31 are quite similar and thus
# handled in one arch
config ARCH_IMX
@@ -74,6 +77,10 @@
bool
select ARM926EJS
+config ARCH_OMAP
+ bool
+# ARM versions used varies on based on OMAP versions
+
choice
prompt "Select your board"
@@ -135,6 +142,12 @@
Say Y here if your are using Phytec's phyCORE-i.MX31 (pcm037) equipped
with a Freescale i.MX31 Processor
+config MACH_OMAP
+ bool "Texas Instruments' OMAP based platforms"
+ select ARCH_OMAP
+ help
+ Say Y if you are using Texas Instrument's OMAP based platforms
+
endchoice
config IMX_CLKO
@@ -144,8 +157,9 @@
The i.MX SoCs have a Pin which can output different reference frequencies.
Say y here if you want to have the clko command which lets you select the
frequency to output on this pin.
-
+
source arch/arm/mach-netx/Kconfig
+source arch/arm/mach-omap/Kconfig
menu "Arm specific settings "
@@ -168,6 +182,13 @@
If you want to start a 2.6 kernel and use an
initrd image say y here.
+config ARMCORTEXA8_DCACHE_SKIP
+ bool "Skip DCache Invlidate"
+ depends on ARMCORTEXA8
+ default n
+ help
+ If your architecture configuration uses some other method of disabling caches, enable this
+ So that the D-Cache invalidation logic is skipped
endmenu
source common/Kconfig
Index: u-boot.v2/arch/arm/Makefile
===================================================================
--- u-boot.v2.orig/arch/arm/Makefile 2008-06-03 20:28:20.000000000 -0500
+++ u-boot.v2/arch/arm/Makefile 2008-06-03 20:42:53.000000000 -0500
@@ -5,6 +5,7 @@
machine-$(CONFIG_ARCH_IMX) := imx
machine-$(CONFIG_ARCH_NETX) := netx
machine-$(CONFIG_ARCH_AT91RM9200) := at91rm9200
+machine-$(CONFIG_ARCH_OMAP) := omap
board-$(CONFIG_MACH_MX1ADS) := mx1ads
board-$(CONFIG_MACH_ECO920) := eco920
board-$(CONFIG_MACH_SCB9328) := scb9328
@@ -12,6 +13,7 @@
board-$(CONFIG_MACH_IMX27ADS) := imx27ads
board-$(CONFIG_MACH_NXDB500) := netx
board-$(CONFIG_MACH_PCM037) := pcm037
+board-$(CONFIG_MACH_OMAP) := omap
# FIXME "cpu-y" never used on ARM!
cpu-$(CONFIG_ARM920T) := arm920t
cpu-$(CONFIG_ARM926EJS) := arm926ejs
@@ -70,6 +72,10 @@
PHONY += maketools
maketools: include/asm-arm/.arch
+# Add architecture specific flags
+ifeq ($(CONFIG_ARMCORTEXA8),y)
+CPPFLAGS += -march=armv7a
+endif
ifneq ($(board-y),)
BOARD := board/$(board-y)/
Index: u-boot.v2/arch/arm/cpu/Makefile
===================================================================
--- u-boot.v2.orig/arch/arm/cpu/Makefile 2008-06-03 20:27:44.000000000 -0500
+++ u-boot.v2/arch/arm/cpu/Makefile 2008-06-03 20:42:53.000000000 -0500
@@ -6,4 +6,5 @@
#
obj-$(CONFIG_ARM920T) += start-arm.o
obj-$(CONFIG_ARM926EJS) += start-arm.o
+obj-$(CONFIG_ARMCORTEXA8) += start-arm.o
obj-$(CONFIG_ARCH_IMX31) += start-arm.o
Index: u-boot.v2/arch/arm/cpu/start-arm.S
===================================================================
--- u-boot.v2.orig/arch/arm/cpu/start-arm.S 2008-06-03 20:42:42.000000000 -0500
+++ u-boot.v2/arch/arm/cpu/start-arm.S 2008-06-03 20:42:53.000000000 -0500
@@ -157,12 +157,66 @@
#ifdef CONFIG_ARCH_HAS_LOWLEVEL_INIT
bl arch_init_lowlevel
#endif
+
+#ifdef CONFIG_ARMCORTEXA8
+ /*
+ * Invalidate v7 I/D caches
+ */
+ mov r0, #0 /* set up for MCR */
+ mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
+ mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
+ /* Invalidate all Dcaches */
+#ifndef CONFIG_ARMCORTEXA8_DCACHE_SKIP
+ /* If Arch specific ROM code SMI handling does not exist */
+ mrc p15, 1, r0, c0, c0, 1 /* read clidr */
+ ands r3, r0, #0x7000000 /* extract loc from clidr */
+ mov r3, r3, lsr #23 /* left align loc bit field */
+ beq finished_inval /* if loc is 0, then no need to clean */
+ mov r10, #0 /* start clean at cache level 0 */
+inval_loop1:
+ add r2, r10, r10, lsr #1 /* work out 3x current cache level */
+ mov r1, r0, lsr r2 /* extract cache type bits from clidr */
+ and r1, r1, #7 /* mask of the bits for current cache only */
+ cmp r1, #2 /* see what cache we have at this level */
+ blt skip_inval /* skip if no cache, or just i-cache */
+ mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
+ isb /* isb to sych the new cssr&csidr */
+ mrc p15, 1, r1, c0, c0, 0 /* read the new csidr */
+ and r2, r1, #7 /* extract the length of the cache lines */
+ add r2, r2, #4 /* add 4 (line length offset) */
+ ldr r4, =0x3ff
+ ands r4, r4, r1, lsr #3 /* find maximum number on the way size*/
+ clz r5, r4 /* find bit position of way size increment */
+ ldr r7, =0x7fff
+ ands r7, r7, r1, lsr #13 /* extract max number of the index size */
+inval_loop2:
+ mov r9, r4 /* create working copy of max way size */
+inval_loop3:
+ orr r11, r10, r9, lsl r5 /* factor way and cache number into r11*/
+ orr r11, r11, r7, lsl r2 /* factor index number into r11 */
+ mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */
+ subs r9, r9, #1 /* decrement the way */
+ bge inval_loop3
+ subs r7, r7, #1 /* decrement the index */
+ bge inval_loop2
+skip_inval:
+ add r10, r10, #2 /* increment cache number */
+ cmp r3, r10
+ bgt inval_loop1
+finished_inval:
+ mov r10, #0 /* swith back to cache level 0 */
+ mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
+ isb
+#endif /* CONFIG_ARMCORTEXA8_DCACHE_SKIP */
+
+#else
/*
* flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
+#endif
/*
* disable MMU stuff and caches
More information about the U-Boot
mailing list