[U-Boot-Users] [patch 0/6] DM9000: Several fixes/cleanups for the DM9000A controller

[Remy Bohmer]

Hello Stefano,

Thanks for testing these patches on the trizeps board. This is very
useful debug info.
I did not expect these problems, but I will continue debugging them.

I assume the problem is caused by patch 05, about fixing the receive
path for DM9000A. Is this correct?
Just to be sure: Does your board contain a DM9000E controller?

It is probably again those little differences between the flavours of
these chips that is killing the driver.
The same reason why the DM9000A did not work, caused the problem why
your chip does not work now...

I will look into it some deeper and come back to you if I have more info.

Kind Regards,

Remy

2008/6/4 Stefano Babic <sbabic at denx.de>:
> Remy Bohmer wrote:
>
>> In a few minutes I will post a patch which I hope it will solve this.
>> Can you please try it on your board?
>
> I have tried, the old error is gone, but the board hangs probably after
> getting the first packets:
>
> $ tftp 0xa0010000 u-boot.bin
> dm9000 i/o: 0x8000000, id: 0x90000a46
>
> DM9000: running in 32 bit mode
>
> MAC: 00:50:c2:3b:8f:0a
>
> operating at 100M full duplex mode
>
> TFTP from server 192.168.2.14; our IP address is 192.168.2.77
>
> Filename 'u-boot.bin'.
> Load address: 0xa0010000
>
> Loading:*
>
> Enabling the debug I get this output (so the first packet was received):
> $  tftp 0xa0010000 u-boot.bin
> eth_halt
>
> phy_write(reg:0x0, value:0x8000)
>
> eth_init()
>
> resetting DM9000
>
> resetting the DM9000, 1st reset
>
> resetting the DM9000, 2nd reset
>
> dm9000 i/o: 0x8000000, id: 0x90000a46
>
> DM9000: running in 32 bit mode
>
> phy_read(0x3): 0x0
>
> MAC: 00:50:c2:3b:8f:0a
>
> 00:50:c2:3b:8f:0a:
>
> phy_read(0x1): 0x7809
>
> phy_read(0x1): 0x7809
>
> phy_read(0x1): 0x7809
>
> phy_read(0x1): 0x7809
>
> phy_read(0x1): 0x7809
>
> phy_read(0x1): 0x7809
>
>
> [snip]
>
> phy_read(0x1): 0x780d
>
> phy_read(0x1): 0x780d
>
> phy_read(0x1): 0x780d
>
> phy_read(0x1): 0x780d
>
>
> [snip]
>
> phy_read(0x1): 0x780d
>
> phy_read(0x1): 0x782d
>
> phy_read(0x11): 0x8018
>
> operating at 100M full duplex mode
>
> TFTP from server 192.168.2.14; our IP address is 192.168.2.77
>
> Filename 'u-boot.bin'.
> Load address: 0xa0010000
>
> Loading: eth_send: length: 42
>
>
>
> eth_send: 00: ff ff ff ff ff ff 00 50
>
> eth_send: 08: c2 3b 8f 0a 08 06 00 01
>
> eth_send: 10: 08 00 06 04 00 01 00 50
>
> eth_send: 18: c2 3b 8f 0a c0 a8 02 4d
>
> eth_send: 20: 00 00 00 00 00 00 c0 a8
>
> eth_send: 28: 02 0e
>
> transmit done
>
>
>
> receiving packet
>
> rx status: 0x0001 rx len: 64
>
> eth_rx: length: 64
>
>
>
> eth_rx: 00: 01 00 40 00 00 50 c2 3b
>
> eth_rx: 08: 8f 0a 00 0b 2b 12 e3 3c
>
> eth_rx: 10: 08 06 00 01 08 00 06 04
>
> eth_rx: 18: 00 02 00 0b 2b 12 e3 3c
>
> eth_rx: 20: c0 a8 02 0e 00 50 c2 3b
>
> eth_rx: 28: 8f 0a c0 a8 02 4d 00 00
>
> eth_rx: 30: 00 00 00 00 00 00 00 00
>
> eth_rx: 38: 00 00 00 00 00 00 00 00
>
> passing packet to upper layer
>
> receiving packet
>
> rx status: 0x806d rx len: 24529
>
>              ^^^          ^^^^^--> wrong
>
> Stefano
>
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