[U-Boot-Users] [PATCH 3/6] AT572D940HF-EB Support
Antonio R. Costa
costa.antonior at gmail.com
Wed Jun 11 14:56:55 CEST 2008
Logic unit: include/asm-arm/arch-at572d940hf (Part 2)
Purpose: AT572D940HF-EB include files (Part 2)
Author: Antnoio R. Costa <antonio.costa <at> atmel.com>
Date : 11 Jun 2008
Status:
- USB,MACB,MCI,DBGU,USARTS working
- Introduced interrput handling on reset to work around
a bug on SDRAM controller
- Introduced a function to compute system frequency at run-time
- Flashes initialised but not recognised
- Environment is built-in and temporarly stored in SDRAM
Signed-off-by: Antonio R. Costa <antonio.costa at atmel.com>
diff --git a/include/asm-arm/arch-at572d940hf/at572d940hf.h b/include/asm-arm/arch-at572d940hf/at572d940hf.h
new file mode 100644
index 0000000..b3e6f77
--- /dev/null
+++ b/include/asm-arm/arch-at572d940hf/at572d940hf.h
@@ -0,0 +1,147 @@
+/*
+ * include/asm-arm/arch-at91/AT572D940HFhf.h
+ *
+ * (C) 2008 Antonio R. Costa
+ *
+ * Common definitions.
+ * Based on AT572D940HFHF datasheet rev A.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT572D940HFHF_H
+#define AT572D940HFHF_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS 1 /* System Peripherals */
+#define AT572D940HF_ID_PIOA 2 /* Parallel IO Controller A */
+#define AT572D940HF_ID_PIOB 3 /* Parallel IO Controller B */
+#define AT572D940HF_ID_PIOC 4 /* Parallel IO Controller C */
+#define AT572D940HF_ID_EMAC 5 /* Ethernet */
+#define AT572D940HF_ID_US0 6 /* USART 0 */
+#define AT572D940HF_ID_US1 7 /* USART 1 */
+#define AT572D940HF_ID_US2 8 /* USART 2 */
+#define AT572D940HF_ID_MCI 9 /* Multimedia Card Interface */
+#define AT572D940HF_ID_UDP 10 /* USB Device Port */
+#define AT572D940HF_ID_TWI 11 /* Two-Wire Interface */
+#define AT572D940HF_ID_TWI0 11 /* Two-Wire Interface */
+#define AT572D940HF_ID_SPI0 12 /* Serial Peripheral Interface 0 */
+#define AT572D940HF_ID_SPI1 13 /* Serial Peripheral Interface 1 */
+#define AT572D940HF_ID_SSC 14 /* Serial Synchronous Controller */
+#define AT572D940HF_ID_SSC0 14 /* Serial Synchronous Controller */
+#define AT572D940HF_ID_SSC1 15 /* Serial Synchronous Controller */
+#define AT572D940HF_ID_SSC2 16 /* Serial Synchronous Controller */
+#define AT572D940HF_ID_TC0 17 /* Timer Counter 0 */
+#define AT572D940HF_ID_TC1 18 /* Timer Counter 1 */
+#define AT572D940HF_ID_TC2 19 /* Timer Counter 2 */
+#define AT572D940HF_ID_UHP 20 /* USB Host port */
+#define AT572D940HF_ID_SSC3 21 /* Serial Synchronous Controller */
+#define AT572D940HF_ID_TWI1 22 /* Two-Wire Interface */
+#define AT572D940HF_ID_CAN0 23 /* CAN Controller */
+#define AT572D940HF_ID_CAN1 24 /* CAN Controller */
+#define AT572D940HF_ID_mHALT 25 /* mAgicV DSP halt int */
+#define AT572D940HF_ID_mSIRQ1 26 /* mAgicV DSP SIRQ1 int */
+#define AT572D940HF_ID_mEXC 27 /* mAgicV DSP Exception int */
+#define AT572D940HF_ID_mEDMA 28 /* mAgicV DSP end of DMA transfer int */
+#define AT572D940HF_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
+#define AT572D940HF_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
+#define AT572D940HF_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
+
+#define AT91_ID_US0 AT572D940HF_ID_US0
+#define AT91_ID_US1 AT572D940HF_ID_US1
+#define AT91_ID_US2 AT572D940HF_ID_US2
+#define AT91_ID_US3 AT572D940HF_ID_US3
+
+#define AT91_ID_UHP AT572D940HF_ID_UHP
+#define AT91_PMC_UHP AT572D940HF_ID_UHP
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT572D940HF_BASE_TCB0 0xfffa0000
+#define AT572D940HF_BASE_TC0 0xfffa0000
+#define AT572D940HF_BASE_TC1 0xfffa0040
+#define AT572D940HF_BASE_TC2 0xfffa0080
+#define AT572D940HF_BASE_UDP 0xfffa4000
+#define AT572D940HF_BASE_MCI 0xfffa8000
+#define AT572D940HF_BASE_TWI 0xfffac000
+#define AT572D940HF_BASE_US0 0xfffb0000
+#define AT572D940HF_BASE_US1 0xfffb4000
+#define AT572D940HF_BASE_US2 0xfffb8000
+#define AT572D940HF_BASE_SSC 0xfffbc000
+#define AT572D940HF_BASE_ISI 0xfffc0000
+#define AT572D940HF_BASE_EMAC 0xfffd8000
+#define AT572D940HF_BASE_SPI0 0xfffc8000
+#define AT572D940HF_BASE_SPI1 0xfffcc000
+#define AT572D940HF_BASE_US3 0xfffd0000
+#define AT572D940HF_BASE_US4 0xfffd4000
+#define AT572D940HF_BASE_US5 0xfffd8000
+#define AT572D940HF_BASE_TCB1 0xfffdc000
+#define AT572D940HF_BASE_TC3 0xfffdc000
+#define AT572D940HF_BASE_TC4 0xfffdc040
+#define AT572D940HF_BASE_TC5 0xfffdc080
+#define AT572D940HF_BASE_ADC 0xfffe0000
+#define AT572D940HF_BASE_RSTC 0xfffffd00
+#define AT91_BASE_SYS 0xffffea00
+
+#define AT91_BASE_EMAC AT572D940HF_BASE_EMAC
+#define AT91_BASE_SPI AT572D940HF_BASE_SPI0
+#define MMCI_BASE AT572D940HF_BASE_MCI
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
+#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
+#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
+#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
+#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
+#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
+
+#define AT91_USART0 AT572D940HF_BASE_US0
+#define AT91_USART1 AT572D940HF_BASE_US1
+#define AT91_USART2 AT572D940HF_BASE_US2
+#define AT91_USART3 AT572D940HF_BASE_US3
+#define AT91_USART4 AT572D940HF_BASE_US4
+#define AT91_USART5 AT572D940HF_BASE_US5
+
+/*
+ * Internal Memory.
+ */
+#define AT572D940HF_ROM_BASE 0x00400000 /* Internal ROM base address */
+#define AT572D940HF_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
+
+#define AT572D940HF_SRAM0_BASE 0x00100000 /* Internal SRAM 0 base address */
+#define AT572D940HF_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (4Kb) */
+#define AT572D940HF_SRAM1_BASE 0x00200000 /* Internal SRAM 0 base address */
+#define AT572D940HF_SRAM1_SIZE SZ_16K /* Internal SRAM 0 size (4Kb) */
+#define AT572D940HF_SRAM2_BASE 0x00300000 /* Internal SRAM 1 base address */
+#define AT572D940HF_SRAM2_SIZE SZ_16K /* Internal SRAM 1 size (4Kb) */
+
+//SDRAM
+#define AT572D940HF_SDRAM_BASE 0x20000000
+
+// USB Host
+#define AT572D940HF_UHP_BASE 0x00500000 /* USB Host controller */
+
+#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */
+#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */
+
+#endif
diff --git a/include/asm-arm/arch-at572d940hf/at572d940hf_matrix.h b/include/asm-arm/arch-at572d940hf/at572d940hf_matrix.h
new file mode 100644
index 0000000..a8e9fec
--- /dev/null
+++ b/include/asm-arm/arch-at572d940hf/at572d940hf_matrix.h
@@ -0,0 +1,78 @@
+/*
+ * include/asm-arm/arch-at91/at91sam9260_matrix.h
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9260 datasheet revision B.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9260_MATRIX_H
+#define AT91SAM9260_MATRIX_H
+
+#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
+#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
+#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
+
+#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
+#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
+#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
+#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
+#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
+#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
+#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
+#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
+
+#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
+#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+
+#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */
+#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91_MATRIX_CS1A_SMC (0 << 1)
+#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
+#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
+#define AT91_MATRIX_CS3A_SMC (0 << 3)
+#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
+#define AT91_MATRIX_CS4A_SMC (0 << 4)
+#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
+#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
+#define AT91_MATRIX_CS5A_SMC (0 << 5)
+#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
+#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
+#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
+#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
+#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
+
+#endif
diff --git a/include/asm-arm/arch-at572d940hf/at572d940hf_mc.h b/include/asm-arm/arch-at572d940hf/at572d940hf_mc.h
new file mode 100644
index 0000000..161d504
--- /dev/null
+++ b/include/asm-arm/arch-at572d940hf/at572d940hf_mc.h
@@ -0,0 +1,140 @@
+/*
+ * include/asm-arm/arch-at91/at91sam926x_mc.h
+ *
+ * Memory Controllers (SMC, SDRAMC) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM926x_MC_H
+#define AT91SAM926x_MC_H
+
+/* SDRAM Controller (SDRAMC) registers */
+#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
+#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
+#define AT91_SDRAMC_MODE_NORMAL 0
+#define AT91_SDRAMC_MODE_NOP 1
+#define AT91_SDRAMC_MODE_PRECHARGE 2
+#define AT91_SDRAMC_MODE_LMR 3
+#define AT91_SDRAMC_MODE_REFRESH 4
+#define AT91_SDRAMC_MODE_EXT_LMR 5
+#define AT91_SDRAMC_MODE_DEEP 6
+
+#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
+#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
+
+#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
+#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
+#define AT91_SDRAMC_NC_8 (0 << 0)
+#define AT91_SDRAMC_NC_9 (1 << 0)
+#define AT91_SDRAMC_NC_10 (2 << 0)
+#define AT91_SDRAMC_NC_11 (3 << 0)
+#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
+#define AT91_SDRAMC_NR_11 (0 << 2)
+#define AT91_SDRAMC_NR_12 (1 << 2)
+#define AT91_SDRAMC_NR_13 (2 << 2)
+#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
+#define AT91_SDRAMC_NB_2 (0 << 4)
+#define AT91_SDRAMC_NB_4 (1 << 4)
+#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
+#define AT91_SDRAMC_CAS_1 (1 << 5)
+#define AT91_SDRAMC_CAS_2 (2 << 5)
+#define AT91_SDRAMC_CAS_3 (3 << 5)
+#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
+#define AT91_SDRAMC_DBW_32 (0 << 7)
+#define AT91_SDRAMC_DBW_16 (1 << 7)
+#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
+#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
+#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
+#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
+#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
+#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
+
+#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
+#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
+#define AT91_SDRAMC_LPCB_DISABLE 0
+#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
+#define AT91_SDRAMC_LPCB_POWER_DOWN 2
+#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
+#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
+#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
+#define AT91_SDRAMC_DS (3 << 10) /* Drive Strenght */
+#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
+#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
+#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
+#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
+
+#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
+#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
+#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
+#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
+#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
+
+#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */
+#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
+#define AT91_SDRAMC_MD_SDRAM 0
+#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
+
+/* Static Memory Controller (SMC) registers */
+#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
+#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
+#define AT91_SMC_NWESETUP_(x) ((x) << 0)
+#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
+#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
+#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
+#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
+#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
+#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
+
+#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
+#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
+#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
+#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
+#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
+#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
+#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
+#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
+#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
+
+#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
+#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
+#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
+#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
+#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
+
+#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
+#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
+#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
+#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
+#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
+#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
+#define AT91_SMC_EXNWMODE_READY (3 << 4)
+#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
+#define AT91_SMC_BAT_SELECT (0 << 8)
+#define AT91_SMC_BAT_WRITE (1 << 8)
+#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
+#define AT91_SMC_DBW_8 (0 << 12)
+#define AT91_SMC_DBW_16 (1 << 12)
+#define AT91_SMC_DBW_32 (2 << 12)
+#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
+#define AT91_SMC_TDF_(x) ((x) << 16)
+#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
+#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
+#define AT91_SMC_PS (3 << 28) /* Page Size */
+#define AT91_SMC_PS_4 (0 << 28)
+#define AT91_SMC_PS_8 (1 << 28)
+#define AT91_SMC_PS_16 (2 << 28)
+#define AT91_SMC_PS_32 (3 << 28)
+
+#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */
+#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
+#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
+#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
+#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-at572d940hf/interrupts.h b/include/asm-arm/arch-at572d940hf/interrupts.h
new file mode 100644
index 0000000..71d3f5d
--- /dev/null
+++ b/include/asm-arm/arch-at572d940hf/interrupts.h
@@ -0,0 +1,41 @@
+/*
+ * include/asm-arm/arch-at572d940/at91_aic.h
+ *
+ * Copyright (C) 2008 Antonio R. Costa
+ * Copyright (C) ATMEL
+ *
+ * Advanced Interrupt Controller (AIC).
+ * Based on AT572D940 datasheet.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __AT572D940_INTERRUPTS_H__
+#define __AT572D940_INTERRUPTS_H__
+
+#include <asm/arch/at91_aic.h>
+
+typedef void (*irq_handler_t) (unsigned long int);
+
+#define SET_IRQ_HANDLER(s,m,h) \
+do { \
+ AIC_WRITE(AIC_SMR(s),m); \
+ AIC_WRITE(AIC_SVR(s),h); \
+ AIC_WRITE(AIC_IECR,(1<<s)); \
+} while(0)
+
+#define RESET_IRQ_HANDLER(s) \
+do { \
+ AIC_WRITE(AIC_SMR(s),0); \
+ AIC_WRITE(AIC_SVR(s),0); \
+ AIC_WRITE(AIC_IDCR,(1<<s)); \
+} while(0)
+
+#define IRQ_ACKNOWLEDGE(n) AIC_WRITE(AIC_EOICR,(n))
+
+extern reset_irqs(void);
+
+#endif /* __AT572D940_INTERRUPTS_H__ */
diff --git a/include/asm-arm/arch-at572d940hf/timer.h b/include/asm-arm/arch-at572d940hf/timer.h
new file mode 100644
index 0000000..8878d06
--- /dev/null
+++ b/include/asm-arm/arch-at572d940hf/timer.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Author: Antonio R. Costa
+ */
+
+#ifndef _AT91_TIMER_H_
+#define _AT91_TIMER_H_
+
+#define AT91_SLOW_FREQ 0
+#define AT91_MAIN_FREQ 1
+#define AT91_PLLA_FREQ 2
+#define AT91_PLLB_FREQ 3
+#define AT91_MASTER_FREQ 4
+#define AT91_SYS_FREQ 4
+#define AT91_PROC_FREQ 5
+
+extern int sys_get_freq(unsigned long mode, unsigned long *pfreq);
+
+#endif /* _AT91_TIMER_H_ */
--
1.5.4.3
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