[U-Boot-Users] [PATCH 08/15 v2] ppc4xx: Add basic support for AMCC 460EX/460GT (4/5)
Stefan Roese
sr at denx.de
Tue Mar 11 17:15:15 CET 2008
This patch adds basic support for the AMCC 460EX/460GT PPC's.
Signed-off-by: Stefan Roese <sr at denx.de>
---
include/common.h | 4 +++-
include/ppc405.h | 23 +++++++++++++++++++----
include/ppc4xx_enet.h | 18 +++++++++++-------
3 files changed, 33 insertions(+), 12 deletions(-)
diff --git a/include/common.h b/include/common.h
index cd8aad0..673afdd 100644
--- a/include/common.h
+++ b/include/common.h
@@ -273,7 +273,9 @@ void pciinfo (int, int);
void pci_master_init (struct pci_controller *);
# endif
int is_pci_host (struct pci_controller *);
-#if defined(CONFIG_440SPE) || defined(CONFIG_405EX)
+#if defined(CONFIG_440SPE) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_405EX)
void pcie_setup_hoses(int busno);
#endif
#endif
diff --git a/include/ppc405.h b/include/ppc405.h
index cbfe89e..37b121c 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -118,7 +118,17 @@
/******************************************************************************
* Universal interrupt controller
******************************************************************************/
+#define UIC_SR 0x0 /* UIC status */
+#define UIC_ER 0x2 /* UIC enable */
+#define UIC_CR 0x3 /* UIC critical */
+#define UIC_PR 0x4 /* UIC polarity */
+#define UIC_TR 0x5 /* UIC triggering */
+#define UIC_MSR 0x6 /* UIC masked status */
+#define UIC_VR 0x7 /* UIC vector */
+#define UIC_VCR 0x8 /* UIC vector configuration */
+
#define UIC_DCR_BASE 0xc0
+#define UIC0_DCR_BASE UIC_DCR_BASE
#define uicsr (UIC_DCR_BASE+0x0) /* UIC status */
#define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */
#define uicer (UIC_DCR_BASE+0x2) /* UIC enable */
@@ -141,6 +151,7 @@
#define uic0vcr uicvcr /* UIC vector configuration*/
#define UIC_DCR_BASE1 0xd0
+#define UIC1_DCR_BASE 0xd0
#define uic1sr (UIC_DCR_BASE1+0x0) /* UIC status */
#define uic1srs (UIC_DCR_BASE1+0x1) /* UIC status set */
#define uic1er (UIC_DCR_BASE1+0x2) /* UIC enable */
@@ -152,6 +163,7 @@
#define uic1vcr (UIC_DCR_BASE1+0x8) /* UIC vector configuration*/
#define UIC_DCR_BASE2 0xe0
+#define UIC2_DCR_BASE 0xe0
#define uic2sr (UIC_DCR_BASE2+0x0) /* UIC status */
#define uic2srs (UIC_DCR_BASE2+0x1) /* UIC status set */
#define uic2er (UIC_DCR_BASE2+0x2) /* UIC enable */
@@ -237,10 +249,13 @@
#define UIC_ENET1 0x00000040 /* */
#define UIC_PCIEMSI2 0x00000020 /* */
#define UIC_EIRQ4 0x00000010 /**/
-#define UIC_UIC2NC 0x00000008 /* */
-#define UIC_UIC2C 0x00000004 /* */
-#define UIC_UIC1NC 0x00000002 /* */
-#define UIC_UIC1C 0x00000001 /* */
+#define UICB0_UIC2NCI 0x00000008 /* */
+#define UICB0_UIC2CI 0x00000004 /* */
+#define UICB0_UIC1NCI 0x00000002 /* */
+#define UICB0_UIC1CI 0x00000001 /* */
+
+#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \
+ UICB0_UIC1CI | UICB0_UIC2NCI)
#define UIC_MAL_TXEOB UIC_MTE/* MAL TXEOB */
#define UIC_MAL_RXEOB UIC_MRE/* MAL RXEOB */
diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h
index 317604a..0208454 100644
--- a/include/ppc4xx_enet.h
+++ b/include/ppc4xx_enet.h
@@ -131,7 +131,7 @@ typedef struct emac_4xx_hw_st {
} EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST;
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_460GT)
#define EMAC_NUM_DEV 4
#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
defined(CONFIG_NET_MULTI) && \
@@ -155,7 +155,8 @@ typedef struct emac_4xx_hw_st {
/* ZMII Bridge Register addresses */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
#else
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
@@ -164,9 +165,6 @@ typedef struct emac_4xx_hw_st {
#define ZMII_SSR (ZMII_BASE + 4)
#define ZMII_SMIISR (ZMII_BASE + 8)
-#define ZMII_RMII 0x22000000
-#define ZMII_MDI0 0x80000000
-
/* ZMII FER Register Bit Definitions */
#define ZMII_FER_DIS (0x0)
#define ZMII_FER_MDI (0x8)
@@ -205,6 +203,8 @@ typedef struct emac_4xx_hw_st {
/* RGMII Register Addresses */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x1000)
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x1500)
#elif defined(CONFIG_405EX)
#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0xB00)
#else
@@ -223,19 +223,21 @@ typedef struct emac_4xx_hw_st {
#define RGMII_FER_V(__x) ((__x - 2) * 4)
+#define RGMII_FER_MDIO(__x) (1 << (19 - (__x)))
+
/* RGMII Speed Selection Register Bit Definitions */
#define RGMII_SSR_SP_10MBPS (0x00)
#define RGMII_SSR_SP_100MBPS (0x02)
#define RGMII_SSR_SP_1000MBPS (0x04)
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
#define RGMII_SSR_V(__x) ((__x) * 8)
#else
#define RGMII_SSR_V(__x) ((__x -2) * 8)
#endif
-
/*---------------------------------------------------------------------------+
| TCP/IP Acceleration Hardware (TAH) 440GX Only
+---------------------------------------------------------------------------*/
@@ -304,7 +306,8 @@ typedef struct emac_4xx_hw_st {
/* Ethernet MAC Regsiter Addresses */
#if defined(CONFIG_440)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00)
#else
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
@@ -345,6 +348,7 @@ typedef struct emac_4xx_hw_st {
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
/* MODE Reg 1 */
#define EMAC_M1_FDE (0x80000000)
--
1.5.4.4
More information about the U-Boot
mailing list