[U-Boot-Users] [PATCH 11/15 v2] ppc4xx: Add AMCC Canyonlands support (460EX) (2/3)
Jean-Christophe PLAGNIOL-VILLARD
plagnioj at jcrosoft.com
Thu Mar 13 00:10:11 CET 2008
On 17:15 Tue 11 Mar , Stefan Roese wrote:
> This patch adds support for the AMCC Canyonlands 460EX evaluation
> board.
>
> Signed-off-by: Stefan Roese <sr at denx.de>
> ---
> include/configs/canyonlands.h | 470 +++++++++++++++++++++++++++++++++++++++++
> 1 files changed, 470 insertions(+), 0 deletions(-)
> create mode 100644 include/configs/canyonlands.h
>
> diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
> new file mode 100644
> index 0000000..6d8f230
> --- /dev/null
> +++ b/include/configs/canyonlands.h
> @@ -0,0 +1,470 @@
> +/*
> + * (C) Copyright 2008
> + * Stefan Roese, DENX Software Engineering, sr at denx.de.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +/************************************************************************
> + * canyonlands.h - configuration for Canyonlands (460EX)
> + ***********************************************************************/
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +/*-----------------------------------------------------------------------
> + * High Level Configuration Options
> + *----------------------------------------------------------------------*/
> +#define CONFIG_CANYONLANDS 1 /* Board is Canyonlands */
> +#define CONFIG_440 1
> +#define CONFIG_4xx 1 /* ... PPC4xx family */
> +#define CONFIG_460EX 1 /* Specific PPC460EX support */
> +
> +#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
> +
> +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
> +#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
> +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
> +
> +/*-----------------------------------------------------------------------
> + * Base addresses -- Note these are effective addresses where the
> + * actual resources get mapped (not physical addresses)
> + *----------------------------------------------------------------------*/
> +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
> +
> +#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
> +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
> +#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
> +
> +#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
> +#define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
> +#define CFG_PCIE_BASE 0xc4000000 /* PCIe UTL regs */
> +
> +#define CFG_PCIE0_CFGBASE 0xc0000000
> +#define CFG_PCIE1_CFGBASE 0xc1000000
> +#define CFG_PCIE0_XCFGBASE 0xc3000000
> +#define CFG_PCIE1_XCFGBASE 0xc3001000
> +
> +#define CFG_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */
> +
> +/* base address of inbound PCIe window */
> +#define CFG_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit physical addr */
> +
> +/* EBC stuff */
> +#define CFG_NAND_ADDR 0xE0000000
> +#define CFG_BCSR_BASE 0xE1000000
> +#define CFG_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */
> +#define CFG_FLASH_BASE 0xFC000000 /* later mapped to this addr */
> +#define CFG_FLASH_BASE_PHYS_H 0x4
> +#define CFG_FLASH_BASE_PHYS_L 0xCC000000
> +#define CFG_FLASH_BASE_PHYS (((u64)CFG_FLASH_BASE_PHYS_H << 32) | \
> + (u64)CFG_FLASH_BASE_PHYS_L)
> +#define CFG_FLASH_SIZE (64 << 20)
> +
> +#define CFG_OCM_BASE 0xE3000000 /* OCM: 16k */
> +#define CFG_SRAM_BASE 0xE8000000 /* SRAM: 256k */
> +#define CFG_LOCAL_CONF_REGS 0xEF000000
> +
> +#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals */
> +
> +#define CFG_MONITOR_BASE TEXT_BASE
> +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
> +#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc()*/
> +
> +/*-----------------------------------------------------------------------
> + * Initial RAM & stack pointer (placed in OCM)
> + *----------------------------------------------------------------------*/
> +#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
> +#define CFG_INIT_RAM_END (4 << 10)
> +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
> +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
> +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
> +
> +/*-----------------------------------------------------------------------
> + * Serial Port
> + *----------------------------------------------------------------------*/
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_SERIAL_MULTI 1
> +#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */
> +
> +#define CFG_BAUDRATE_TABLE \
> + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
> +
> +/*-----------------------------------------------------------------------
> + * Environment
> + *----------------------------------------------------------------------*/
> +/*
> + * Define here the location of the environment variables (FLASH).
> + */
> +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
> +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
> +#define CFG_NAND_CS 3 /* NAND chip connected to CSx */
> +#else
> +#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
> +#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
> +#endif
> +
> +/*-----------------------------------------------------------------------
> + * FLASH related
> + *----------------------------------------------------------------------*/
> +#define CFG_FLASH_CFI /* The flash is CFI compatible */
> +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
> +#define CFG_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
> +
> +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
> +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
> +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
> +
> +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
> +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
> +
> +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
> +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
> +
> +#ifdef CFG_ENV_IS_IN_FLASH
> +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
^
Whitespace please remove
> +#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
> +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
> +
> +/* Address and size of Redundant Environment Sector */
> +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
> +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
> +#endif /* CFG_ENV_IS_IN_FLASH */
> +
> +/*-----------------------------------------------------------------------
> + * NAND-FLASH related
> + *----------------------------------------------------------------------*/
> +#define CFG_MAX_NAND_DEVICE 1
> +#define NAND_MAX_CHIPS 1
> +#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
> +#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
> +
> +/*------------------------------------------------------------------------------
> + * DDR SDRAM
> + *----------------------------------------------------------------------------*/
> +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
> +#define SPD_EEPROM_ADDRESS {0x50, 0x51} /* SPD i2c spd addresses*/
> +#define CONFIG_DDR_ECC 1 /* with ECC support */
> +#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */
> +
> +/*-----------------------------------------------------------------------
> + * I2C
> + *----------------------------------------------------------------------*/
> +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
> +#undef CONFIG_SOFT_I2C /* I2C bit-banged */
> +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
> +#define CFG_I2C_SLAVE 0x7F
> +
> +#define CFG_I2C_MULTI_EEPROMS
> +#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
> +#define CFG_I2C_EEPROM_ADDR_LEN 1
^
Whitespace please remove
> +#define CFG_EEPROM_PAGE_WRITE_ENABLE
> +#define CFG_EEPROM_PAGE_WRITE_BITS 3
> +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
> +
Best Regards,
J
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