[U-Boot-Users] [PATCH] ppc4xx: Don't use last 256 bytes of SDRAM, workaround for 440EPx CHIP 11 errata

[Stefan Roese]

Hi Larry,

On Thursday 20 March 2008, Larry Johnson wrote:
> Having multiple implementations of the 440EXp SDRAM setup code is, in
> itself, less than ideal.  One alternative is to have a 440EPX board with
> on-board SDRAM chips fake an array of SPD bytes describing the chips,
> and pass it to the "denali_spd_ddr2.c" code.  The SPD code then becomes
> the single location for the technology of how to configure the Denali
> SDRAM controller.

Generally a good idea. Unfortunately it can't be done. Think about 440EPx 
boards booting from NAND flash. Here the complete CPU setup code including 
SDRAM setup needs to fit into 4k. This can only be done with a fixed SDRAM 
setup. :-(

But your are right. Other boards without such a image size restriction should 
probably use the SPD code. One reason they aren't doing it right now is, that 
the SPD code is quite new and didn't exist when those board port were done. 
But they can be converted to use this code at some time.

> The additional benefit (for me, anyway :-) ) is having more eyeballs on
> the SPD code, with more opportunities for testing, bug fixing, and
> enhancements.

Ack.

BTW: Can you test your board with ECC modules? We need to change the ECC code 
in the Denali SPD routines to not touch the last 256 bytes here too. Best 
would be if you could provide a patch for this. :)

Thanks.

Best regards,
Stefan

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