[U-Boot-Users] Fwd: Xilinx Spartan3 CRC error during FPGA load

[Tales Toledo]

Hi,

 does anybody have a CRC problem programming Xilinx Spartan3 in slave
 serial mode?
 I'm using u-boot-1.3.0 with Matthias suggested changes in bit swapping
 and always get the same error.
 The .bit is ok since it was programmed using JTAG and works fine.
 The command sequence and u-boot debug messages are below for reference.
 Any suggestion is appreciated.

 Thx,
 TT

 => tftp 100000 fpganew.bit
 Using FEC ETHERNET device
 TFTP from server 192.168.1.100; our IP address is 192.168.1.1
 Filename 'fpganew.bit'.
 Load address: 0x100000
 Loading: #########
 done
 Bytes transferred = 131034 (1ffda hex)
 => fpga loadb 0 100000 ${filesize}
 do_fpga: fpga_data = 0x100000
 do_fpga: device = 0
  design filename = "fpga_top.ncd"
  part number = "3s200tq144"
  date = "2008/ 3/25"
  time = "16:37:58"
  bytes in bitstream = 130952
 fpga_get_desc: found fpga descriptor #0 @ 0x01ffad04
 Spartan3_load: Launching Slave Serial Load
 Spartan3_ss_load: start with interface functions @ 0x01ff8c00
 Spartan3_ss_load: Function Table:
 ptr:    0x01bb6a90
 struct: 0x01ff8c00
 pgm:    0x01febf80
 init:   0x01fec000
 clk:    0x01fec0e8
 wr:     0x01fec118
 done:   0x01fec070

 Loading FPGA Device 0...
 fpga_pre_fn:111: FPGA pre-configuration
 fpga_pgm_fn:122: FPGA PROGRAM asserted
 fpga_init_fn:145: INIT check... low
 fpga_pgm_fn:122: FPGA PROGRAM deasserted
 fpga_init_fn:145: INIT check... high
 ........................................fpga_init_fn:145: INIT check... high
 fpga_init_fn:145: INIT check... low
 ** CRC error during FPGA load.
 bytecount=130938, bsize=130952