[U-Boot-Users] [U-Boot Users][PATCH] ADS5121 Rev 3 Configuration Changes
Martha J Marx
mmarx at silicontkx.com
Sat May 3 23:14:18 CEST 2008
Configuration changes added to support ADS5121 Rev 3 version of the board.
This includes changes to the ref clock, memory size (from 256 to 512), the
addition of PCI functionality and Makefile options to build either the Rev 3
or Rev 2 U-Boot. The new README explains these options.
Signed-off-by: Martha J Marx <mmarx at si...>
---
Makefile | 9 ++++-----
board/ads5121/README | 9 +++++++++
board/ads5121/ads5121.c | 34 ++++++++++++++++++++++++++++++----
cpu/mpc512x/cpu.c | 8 ++++++--
include/configs/ads5121.h | 27 +++++++++++++++++++++++----
5 files changed, 72 insertions(+), 15 deletions(-)
create mode 100644 board/ads5121/README
diff --git a/Makefile b/Makefile
index ac0a17f..f91c75b 100644
--- a/Makefile
+++ b/Makefile
@@ -742,12 +742,11 @@ motionpro_config: unconfig
## MPC512x Systems
#########################################################################
ads5121_config \
-ads5121_PCI_config \
- : unconfig
+ads5121_256_config \
+ : unconfig
@mkdir -p $(obj)include
- @if [ "$(findstring _PCI_,$@)" ] ; then \
- echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
- $(XECHO) "... with PCI enabled" ; \
+ @if [ "$(findstring 256,$@)" ] ; then \
+ echo "#define CONFIG_ADS5121_256 1" >
$(obj)include/config.h; \
fi
@$(MKCONFIG) -a ads5121 ppc mpc512x ads5121
diff --git a/board/ads5121/README b/board/ads5121/README
new file mode 100644
index 0000000..ec49ba8
--- /dev/null
+++ b/board/ads5121/README
@@ -0,0 +1,9 @@
+To configure for the Rev 3.x ADS5121 type
+make ads5121_config
+This will automatically include PCI and the Real Time CLock abilities,
+and set the correct frequency and memory configuration.
+
+To configure for the Rev 2 ADS5121 type
+make ads5121_256_config
+
+
diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c
index 8629b03..35544f1 100644
--- a/board/ads5121/ads5121.c
+++ b/board/ads5121/ads5121.c
@@ -26,7 +26,9 @@
#include <asm/bitops.h>
#include <command.h>
#include <fdt_support.h>
-
+#ifdef CONFIG_MISC_INIT_R
+#include <i2c.h>
+#endif
/* Clocks in use */
#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN |
\
CLOCK_SCCR1_LPC_EN | \
@@ -50,7 +52,6 @@ int board_early_init_f (void)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
u32 lpcaw;
-
/*
* Initialize Local Window for the CPLD registers access (CS2
selects
* the CPLD chip)
@@ -58,7 +59,6 @@ int board_early_init_f (void)
im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) |
CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE);
im->lpc.cs_cfg[2] = CFG_CS2_CFG;
-
/*
* According to MPC5121e RM, configuring local access windows should
* be followed by a dummy read of the config register that was
@@ -73,8 +73,22 @@ int board_early_init_f (void)
* Without this the flash identification routine fails, as it needs
to issue
* write commands in order to establish the device ID.
*/
- *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
+#ifdef CONFIG_ADS5121_256
+ *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
+#else
+ if (*((u8 *)(CFG_CPLD_BASE + 0x08)) & 0x04) {
+
+ *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
+ } else {
+ /* running from Backup flash */
+ *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0x32;
+ }
+#endif
+ /*
+ * Configure Flash Speed
+ */
+ *((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) =
CFG_CS0_CFG;
/*
* Enable clocks
*/
@@ -203,6 +217,18 @@ int checkboard (void)
reg[i] |= 0x00000003;
return 0;
}
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ /*
+ * I2C writes to turn on DVI
+ */
+ static uchar buf[1] = {0xbf};
+ i2c_set_bus_num(2);
+ i2c_write(0x38, 0x8, 1, buf, 1);
+ return 0;
+}
+#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c
index bed77ac..3b45bfe 100644
--- a/cpu/mpc512x/cpu.c
+++ b/cpu/mpc512x/cpu.c
@@ -133,8 +133,9 @@ void watchdog_reset (void)
#ifdef CONFIG_OF_LIBFDT
void ft_cpu_setup(void *blob, bd_t *bd)
{
- char * cpu_path = "/cpus/" OF_CPU;
- char * eth_path = "/" OF_SOC "/ethernet at 2800";
+ char *cpu_path = "/cpus/" OF_CPU;
+ char *eth_path = "/" OF_SOC "/ethernet at 2800";
+ char *eth_path_old = "/" OF_SOC_OLD "/ethernet at 2800";
do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK,
1);
do_fixup_by_path_u32(blob, cpu_path, "bus-frequency",
bd->bi_busfreq, 1);
@@ -143,6 +144,9 @@ void ft_cpu_setup(void *blob, bd_t *bd)
do_fixup_by_path(blob, eth_path, "local-mac-address",
bd->bi_enetaddr, 6, 0);
/* this is so old kernels with old device trees will boot */
+
do_fixup_by_path_u32(blob, "/" OF_SOC_OLD, "bus-frequency",
bd->bi_ipsfreq, 0);
+ do_fixup_by_path(blob, eth_path_old, "local-mac-address",
bd->bi_enetaddr, 6, 0);
+ do_fixup_by_path(blob, eth_path_old, "address", bd->bi_enetaddr, 6,
0);
}
#endif
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
index 81e7c1e..5f82855 100644
--- a/include/configs/ads5121.h
+++ b/include/configs/ads5121.h
@@ -48,9 +48,15 @@
/* CONFIG_PCI is defined at config time */
+#ifdef CONFIG_ADS5121_256
#define CFG_MPC512X_CLKIN 66000000 /* in Hz */
+#else
+#define CFG_MPC512X_CLKIN 33333333 /* in Hz */
+#define CONFIG_PCI
+#endif
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f()
*/
+#define CONFIG_MISC_INIT_R /* call
board_last_stage_init() */
#define CFG_IMMR 0x80000000
@@ -60,7 +66,11 @@
/*
* DDR Setup - manually set all parameters as there's no SPD etc.
*/
+#ifdef CONFIG_ADS5121_256
#define CFG_DDR_SIZE 256 /* MB */
+#else
+#define CFG_DDR_SIZE 512 /* MB */
+#endif
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
#define CFG_SDRAM_BASE CFG_DDR_BASE
@@ -108,14 +118,20 @@
* [09:05] DRAM tRP:
* [04:00] DRAM tRPA
*/
-
+#ifdef CONFIG_ADS5121_256
#define CFG_MDDRC_SYS_CFG 0xF8604A00
#define CFG_MDDRC_SYS_CFG_RUN 0xE8604A00
+#define CFG_MDDRC_TIME_CFG1 0x54EC1168
+#define CFG_MDDRC_TIME_CFG2 0x35210864
+#else
+#define CFG_MDDRC_SYS_CFG 0xFA804A00
+#define CFG_MDDRC_SYS_CFG_RUN 0xEA804A00
+#define CFG_MDDRC_TIME_CFG1 0x68EC1168
+#define CFG_MDDRC_TIME_CFG2 0x34310864
+#endif
#define CFG_MDDRC_SYS_CFG_EN 0xF0000000
#define CFG_MDDRC_TIME_CFG0 0x00003D2E
#define CFG_MDDRC_TIME_CFG0_RUN 0x06183D2E
-#define CFG_MDDRC_TIME_CFG1 0x54EC1168
-#define CFG_MDDRC_TIME_CFG2 0x35210864
#define CFG_MICRON_NOP 0x01380000
#define CFG_MICRON_PCHG_ALL 0x01100400
@@ -175,8 +191,11 @@
#define CFG_SRAM_BASE 0x30000000
#define CFG_SRAM_SIZE 0x00020000 /* 128 KB */
-
+#ifdef ADS5121_256_CONFIG
#define CFG_CS0_CFG 0x05059310 /* ALE active low, data size
4bytes */
+#else
+#define CFG_CS0_CFG 0x05059310 /* ALE active low, data size
4bytes */
+#endif
#define CFG_CS2_CFG 0x05059010 /* ALE active low, data size
1byte */
/* Use SRAM for initial stack */
--
1.5.2.4
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