[U-Boot-Users] [PATCH] 7450 and 86xx L2 cache invalidate bug corrections

[Jon Loeliger]

On Fri, 2008-05-02 at 13:35 -0700, Wheatley Travis wrote:
>  
> The 7610 and related parts have an L2IP bit in the L2CR that is
> monitored to signal when the L2 cache invalidate is complete whereas the
> 7450 and related parts utilize L2I for this purpose. However, the
> current code does not account for this difference. Additionally the 86xx
> L2 cache invalidate code used an "andi" instruction where an "andis"
> instruction should have been used.
> 
> This patch addresses both of these bugs.
> 
> 
> Signed-off-by: Travis Wheatley <travis.wheatley at freescale.com>
> ---
>  cpu/74xx_7xx/cache.S |   21 ++++++++++++++++++++-
>  cpu/mpc86xx/cache.S  |    2 +-
>  2 files changed, 21 insertions(+), 2 deletions(-)


Acked-By: Jon Loeliger <jdl at freescale.com>