[U-Boot-Users] bugs in flush_cache

[Eyal Bari]

in your version of the function the iterated cache ops second argument was
start_addr which stay constant.

the second bug is that it doesn't iterate over the entire range:
for example:
if size is 42 and the cache line size is 32 - it takes two cache lines to
cache this buffer
your version will iterate only over one cache line
my version will iterate over two cache line covering the entire range

eyalb

On Tue, May 13, 2008 at 4:19 PM, Shinya Kuribayashi <skuribay at ruby.dti.ne.jp>
wrote:

> Eyal Bari wrote:
>
> > hi,
> >
> > i found two bugs in your flush_cache routine:
> > * it was only flushing the first cacheline in the range
> > * the loop was running one cacheline short
> >
> > the fixed version:
> > void flush_cache(ulong start_addr, ulong size)
> > {
> >    unsigned long lsize = CFG_CACHELINE_SIZE;
> >    unsigned long addr = start_addr & ~(lsize - 1);
> >    unsigned long aend = (start_addr + size - 1 + lsize) & ~(lsize - 1);
> >
> >    while (1) {
> >        cache_op(Hit_Writeback_Inv_D, addr);
> >        cache_op(Hit_Invalidate_I, addr);
> >        if (addr == aend)
> >            break;
> >        addr += lsize;
> >    }
> > }
> >
> > eyalb
> >
>
> Really? I don't think so.
>
> See Linux's include/asm-mips/r4kcache.h#413. This is the original.
>
>
> http://git.kernel.org/?p=linux/kernel/git/ralf/linux.git;a=blob;f=include/asm-mips/r4kcache.h;h=4c140db3678655975d2dde877d898a5f9861ad6e;hb=HEAD#l413
>
>  Shinya
>
> P.S. If you don't mind, please add Cc: u-boot-users when replying.
>
>
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