[U-Boot-Users] [PATCH] PPC40x: Rework CFG_INIT_DCACHE_CS Block to Avoid Machine Checks

[Wolfgang Denk]

In message <C455E5F6.F3FB%gerickson at nuovations.com> you wrote:
>
> >> +  * For boards that don't have OCM and can't use the data cache
> >> +  * for their primordial stack, setup stack here directly after the
> >> +  * SDRAM is initialized in ext_bus_cntlr_init.
> > 
> > Was there ever a useful explanation given why these boards should not
> > be able to use DC as initial RAM?
> 
> Kilauea, Makalu and Haleakala (405EX- and 405EXr-based) can now use the data
> cache for the initial stack and data area with this 'dcba' change patch.
> 
> However, no clear reason has been provided as yet from the vendor as to why
> the 'dcba' addition was not historically required for the 405GP but is
> required now for the 405EX[r]. Regardless, the 'dcba' should work and, going
> forward, will be "more correct" on the 405GP as well.

So the comment "can't use the data cache for their primordial stack"
is wrong and should be fixed?

Best regards,

Wolfgang Denk

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